Semiconductor device manufacturing: process – Forming bipolar transistor by formation or alteration of... – Including passive device
Reexamination Certificate
2001-06-29
2003-03-04
Chaudhuri, Olik (Department: 2814)
Semiconductor device manufacturing: process
Forming bipolar transistor by formation or alteration of...
Including passive device
C438S210000, C438S382000
Reexamination Certificate
active
06528380
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to the field of semiconductor manufacturing, and more specifically to a n-well resistor and its method of fabrication.
BACKGROUND OF THE INVENTION
One important aspect of product development in the semiconductor industry relates to the quality and reliability of integrated circuit devices. It is well known that the accumulation of static charge can lead to extremely high voltages developed near an integrated circuit (IC). Electrostatic discharge (ESD) refers to the phenomenon of the electrical discharge of high current for short duration. This current could be the result of the static charge build up on a particular IC package or on a nearby human being handling that particular IC package. ESD is a serious problem for semiconductor devices since it has the potential to destroy an entire integrated circuit. Because ESD events often occur across the circuits attached to the package nodes, circuit designers have concentrated their efforts on developing adequate protection mechanisms for these sensitive circuits. Ideally, an ESD device should be able to protect an IC against any conceivable static discharge by passing large currents in a short time in a non-destructive manner.
N-well resistors are used as part of the electrostatic discharge (ESD) scheme in complementary metal oxide semiconductor (CMOS) integrated circuits. Presently in the current state of the art, the solution uses a high resistance n-well ballast resistor formed under isolation in pinched n-well.
A conventional n-well resistor constructed with an isolation structure is shown in
FIGS. 1A and 1B
.
FIG. 1A
is an illustration of an overhead view of a conventional n-well resistor device
101
formed with a shallow trench isolation (STI) structure
108
together with an n-type metal oxide semiconductor (NMOS) transistor device
113
.
FIG. 1B
is an illustration of a cross-sectional view of the conventional n-well resistor device
101
and NMOS transistor
113
of
FIG. 1A
along elevation A. Resistor
101
includes a first n+ polysilicon region
104
and a second n+ polysilicon region
110
formed on an n-type silicon region
106
. These two n+ diffusion regions
104
,
110
are the two ends of the resistor
101
. An isolation structure, a shallow trench isolation (STI) structure
108
here, is used to form the n-well resistor
101
by blocking salicide formation between the first
104
and second
110
poly regions. Silicide is formed when metal reacts with silicon. The STI structure of this n-well resistor controls the diffusion and isolates the two terminals
103
,
109
of the resistor
101
. Hence, silicide does not form on the STI
108
. N+ silicide
103
,
109
is formed on top of the poly regions
104
,
110
. The STI
108
is formed inside the n-well
106
and consumes a portion of the n-well. This arrangement is known as a pinched well and results in higher sheet resistance of the overall resistor structure.
An NMOS transistor
113
is shown with this resistor
101
. N-type transistor
113
comprises an n+ polysilicon gate
112
formed on a dielectric with is form on a p-type silicon region
120
. A pair of n+ source/drain regions
118
,
111
are formed along laterally opposite sidewalls of polysilicon gate
112
. N-type tip regions extend out from the source/drain regions
118
,
111
and underneath the polysilicon gate
112
. Transistor
113
also includes a pair of spacers formed along laterally opposite sidewalls of the polysilicon/dielectric stack. Also formed on the source/drain regions
118
,
111
, and the poly gate
112
is silicide
115
,
117
,
119
.
The n-well resistor device
101
is coupled to the NMOS transistor
113
. The two polycide regions
103
,
109
serve as the two terminals of the resistor
101
. One end
109
of the resistor
101
is coupled to the drain
115
of the NMOS device
113
here.
During an electrostatic discharge (ESD) event, a phenomenon known as snap-back occurs with the NMOS device. A high current can flow through the device during the event an cause a catastrophic failure. The resistor
101
serves to limit the amount of current conducted and to distribute current across the channel. The conventional n-well resistor
101
described above causes current to flow from the drain terminal
115
of the NMOS device
113
to one end
109
of the resistor
101
and over to the other end
103
. But the current path in this resistor
101
comprises an X component (horizontal) and a Y component (vertical). A pinched area is created in the n-well
106
under the STI
108
. The STI structure
108
prevents current from flowing in a straight path from the diffusion at one end
109
of the resistor
101
to the diffusion at the other end
103
. The current has to go around the STI structure
108
by traveling down in the n-well
106
, under the STI
108
, and back up through the n-well
106
.
While these pinched n-well resistors fulfill the needs of previous technologies, newer semiconductor processing techniques have introduced another issue. The smaller device dimensions of for new semiconductor technologies have significant current causes a reduction in the horizontal dimension of the current path through the n-well resistor. Meanwhile, the vertical component of the current path becomes more dominant. However, the horizontal component of a resistor is more important because that dimension can be controlled. Generally, the longer the resistor, the greater the resistance.
But in new process technologies, the horizontal component of the current path got smaller while the vertical component was not affected. Even though the depth or vertical component did not adversely affect the operation of the resistor, designer do not have good control over the depth. As the new process technologies reduced device dimensions, transistors got smaller, but resistors did not. In order to compensate for the reduced resistance, larger resistor devices had to be constructed to compensate.
The semiconductor process technology had another effect on resistor. The amount of resistance available from a resistor could vary on the order of 50% from one process technology to another. Designers should have better control of circuit impedance without such large variations.
SUMMARY OF THE INVENTION
An n-well resistor device and its method of fabrication is described. The n-well resistor device of the present invention comprises a first n-type region and a second n-type region formed in an n-type silicon region. A gate dielectric layer formed on said n-type silicon region. A polysilicon gate formed on said gate dielectric.
Other features and advantages of the present invention will be apparent from the accompanying drawings and from the detailed description that follow below.
REFERENCES:
patent: 3577019 (1971-05-01), Storm
patent: 4406997 (1983-09-01), Depp et al.
patent: 5019888 (1991-05-01), Scott et al.
patent: 5637902 (1997-06-01), Jiang
patent: 5705417 (1998-01-01), Tseng
patent: 5952701 (1999-09-01), Bulucea et al.
patent: 6034388 (2000-03-01), Brown et al.
Ilkbahar Alper
Woolery Bruce
Chaudhuri Olik
Lam Peter
Nguyen Dilinh
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