Electro-static discharge protection circuit with bimodal resista

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

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Details

257355, 257356, 257360, H01L 2906, H01L 2978, H01L 2702

Patent

active

052705650

ABSTRACT:
An electrostatic discharge protection circuit employing an extended resistive structure having bimodal resistance characteristics in series with an input/output buffer circuit and an input/output electrical contact pad on an integrated circuit. The extended resistive structure is integrally formed with the device or devices in the buffer circuit most susceptible to damage due to ESD breakdown effects In a first resistance mode during normal circuit operations, the resistor has a low resistance value and introduces virtually no additional load to the input/output buffer circuitry. In a second mode of operation during ESD discharge, the resistor has a second significantly higher resistance which reduces current values during the ESD event thereby protecting the buffer circuit. Thick oxide snap-back device is also employed to provide a parallel ESD discharge path with low power dissipation.

REFERENCES:
patent: 4086642 (1978-04-01), Yoshida et al.
patent: 4605980 (1986-08-01), Hartranft et al.
patent: 4868621 (1989-09-01), Miyamoto
patent: 4896243 (1990-01-01), Chatterjee et al.
patent: 4897368 (1990-01-01), Kobushi et al.
patent: 5019888 (1991-05-01), Scott et al.
patent: 5060037 (1991-10-01), Rountree
Chen, et al. "The Effect of Channel Hot Carrier Stressing on Gate Oxide Integrity in MOSFET", Proc. Int'l Reliability Physics Symposium, (1988), pp. 1-7.
Khurana, et al., "ESD on CHMOS Devices--Equivalent Circuits, Physical Models and Failure Mechanisms", Proc. Int'l Reliability Physics Symposium, (1985) pp. 212-223.
Duvvury, et al., "ESD Protection Reliability in 1 Micrometer CMOS Technologies", Proc. Int'l Reliability Physics Symposium (1986) pp. 199-205.
Weste, et al., Principles of CMOS VLSI Design, Addison-Wesley Publishing Company pp. 224-231.
Fujishin, et al., "Optimized ESD Protection Circuits for High-Speed MOS/VLSI", Proc. Custom Integrated Circuits Conference May, 1984, pp. 569-573.
Ochoa, et al., "Snap-Back: A Stable Regenerative Breakdown Mode of MOS Devices", IEEE Transactions on Nuclear Science, vol. NS-30, No. 6, Dec., 1983, pp. 4127-4130.
Avery, "Using SCR's As Transient Protection Structures in Integrated Circuits", RCA DSRC, Princeton, N.J., pp. 177-180.

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