Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-09-22
2002-04-02
Lee, Eddie (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S328000, C257S351000, C257S355000, C257S356000, C257S546000, C438S212000, C438S223000, C438S224000, C438S227000, C438S268000
Reexamination Certificate
active
06365941
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to an electro-static discharge (ESD) circuit, and more particularly to an enhanced ESD circuit, a structure thereof and a method for fabricating the structure.
DESCRIPTION OF THE RELATED ART
A semiconductor device includes, in general as a protection circuit, an electro-static discharge circuit which enables it to temporarily withstand a large amount of externally applied voltage (for example, several thousand volts). An electro-static discharge circuit is interposed between a pad and an internal circuit of a semiconductor device. When a voltage exceeding an appropriate operating range is applied to a pad of a semiconductor device, an electro-static discharge circuit protects an internal circuit of the semiconductor device by allowing electrostatic charge induced in the pad to bypass the internal circuit through a power pad (Vcc pad) or a ground pad.
When a voltage of several thousands volts is momentarily applied to a pad, a large amount of electro-static charge is generated. If the electro-static charge does not rapidly by-pass the internal circuit, damage occurs to the internal circuit. Thus, conventionally, a diode is formed between a pad and a semiconductor substrate, and the electro-static charge induced in the pad is discharged by using a reverse breakdown current of the diode. Here, if a junction area of the diode is small, current density of the electro-static charge discharging through the junction of the diode increases. As a result, the junction of the diode is susceptible to damage.
Thus, a conventional ESD circuit requires a diode having a very large junction area. Also, in conventional ESD circuits, if the reverse breakdown current is greater than a predetermined current level, the junction of the diode is easily damaged. Therefore, in an ESD circuit adopting a general diode, it is difficult to improve the characteristics of the ESD circuit unless the junction area of the diode is maximized. In particular, semiconductor devices for driving liquid crystal display devices use a high operating voltage of 10 volts or higher, unlike conventional semiconductor memory devices. Thus, a high voltage semiconductor device using a high operating voltage of 10 volts or higher should have a breakdown voltage of a source/drain region of a MOS transistor higher than the operating voltage. Accordingly, it is desirable to minimize impurity concentrations of the source/drain region and a well in which the MOS transistor is formed. However, it is typical for a junction diode used in an ESD circuit of a high voltage semiconductor device to be simultaneously formed with a source/drain region of a MOS transistor.
FIG. 20
is an equivalent circuit diagram of a conventional ESD circuit. Referring to
FIG. 20
, a diode CD is interposed between a pad P and a grounded semiconductor substrate. A P-type electrode and an N-type electrode of the diode CD are connected to a ground terminal and the pad P, respectively. Also, the pad P is connected to an internal circuit. Here, a reverse breakdown voltage of the diode CD must be higher than an operating voltage of the internal circuit. Thus, if a voltage lower than the operating voltage of the internal circuit and higher than a ground voltage is applied to the pad P, the voltage applied to the pad P makes the internal circuit operate normally. In this way, if a voltage higher than the operating voltage of the internal circuit or a negative voltage is applied to the pad P, charges induced in the pad P are by-passed through the diode CD. Accordingly, the internal circuit can be protected from excessive currents.
FIG. 21
is a vertical sectional view of a structure in which the ESD circuit in
FIG. 20
is implemented in a semiconductor substrate. Referring to
FIG. 21
, isolation layers
303
defining active regions are formed in predetermined regions of a semiconductor substrate
301
. For example, a P-type semiconductor substrate, an impurity region doped with impurities of a conductivity type opposite to that of the semiconductor substrate
301
, i.e., an N-type impurity region, is formed in one of the active regions between the isolation layers
303
. The N-type impurity region consists of a heavily doped N-type impurity region
307
and a lightly doped N-type impurity region
305
surrounding the heavily doped N-type impurity region
307
. The N-type impurity region is simultaneously formed with a source/drain region of a high voltage NMOS transistor. Also, an impurity region doped with impurities of the same conductivity as that of the semiconductor substrate
301
, that is, a P-type impurity region
309
, is formed in an active region adjacent to the N-type impurity region. The P-type impurity region
309
serves as a pick-up area for applying a bias voltage, i.e., a ground potential, to the semiconductor substrate
301
. The isolation layers
303
and the active regions are covered by an interlayer dielectric film. The heavily doped N-type impurity region
307
constituting the N-type impurity region is connected to a pad electrode
313
P passing through a predetermined area of the interlayer dielectric film
311
, and the P-type impurity region
309
is connected to ground pads
313
G passing through a predetermined area of the interlayer dielectric film
311
. Therefore, the N-type impurity region and the semiconductor substrate
301
correspond to an N-type electrode and a P-type electrode of the diode CD shown in
FIG. 20
, respectively.
According to the above-described conventional technology, the characteristics of an ESD circuit are directly affected by a junction area of a diode. As the area where the N-type impurity region and the semiconductor substrate contact is increased, the electro-static discharge characteristics, that is, the ESD voltages, increase. However, the integration density of a semiconductor device is relatively reduced.
Therefore, in a conventional ESD circuit of a semiconductor device, it is desired to improve the electrostatic discharge characteristics of the ESD circuit without rendering the integration density of the semiconductor device reduced.
SUMMARY OF THE INVENTION
To solve the above and other problems, it is an object of the present invention to provide an electrostatic discharge circuit of a semiconductor device which can protect a junction diode connected to a pad from being damaged.
It is another object of the present invention to provide a structure of the electro-static discharge circuit.
It is still another object of the present invention to provide a method for fabricating the structure of the electro-static discharge circuit.
Accordingly, to achieve the first object, the present invention provides an electro-static discharge (ESD) circuit of a semiconductor device having a ground pad, a power pad, a plurality of electrical signal pads and an internal circuit, the ESD circuit including at least one MOS transistor having a gate electrode and a drain region connected to each of the electrical signal pads; and a Zener diode connected to a source region of the at least one MOS transistor.
According to another aspect of the present invention, there is provided an electro-static discharge (ESD) circuit of a semiconductor device having a ground pad, a power pad, a plurality of electrical signal pads and a plurality of internal circuits each having an input terminal, the ESD circuit including a MOS transistor having a gate electrode and a drain region connected to each of the electrical signal pads, and a common diode connected to a source region of the MOS transistor.
To achieve the second object, the present invention provides an electro-static discharge (ESD) structure of a semiconductor device including a gate electrode formed on a predetermined area of a semiconductor substrate of a first conductivity type, a lightly doped source region of a second conductivity type and a lightly doped drain region of the second conductivity type which are formed in the semiconductor substrate at both sides of the gate electrode, respectively, a heavily doped dege
Lee Eddie
Warren Matthew E.
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