Patent
1988-07-20
1990-07-03
Laroche, Eugene R.
350355, G02F 101, G02F 1133
Patent
active
049385674
DESCRIPTION:
BRIEF SUMMARY
The invention concerns an electro-optical display panel with control transistors and, more particularly, a flat panel in which each pixel to be displayed is controlled by a transistor. It can be applied to the making of large-area liquid crystal flat panels, the control transistors of which are made by integration in the form of thin layers. The method according to the invention enables the making of a panel by a redundant method with a minimum number of lithographic masks.
As is known, these panels generally have a large number of elementary points or pixels which are square-shaped or rectangular. These pixels should be addressed individually. The definition of the panel depends on the number of point capable of receiving a piece of information. Each point is controlled by applying an electrical field through the liquid crystal. To display alphanumerical or graphic data, matrix-type displays have been proposed. Each pixel is then defined by the intersection of two networks of orthogonal conductors called lines and columns.
The addressing of these matrix display panels is becoming increasingly important as it being sought to increase their definition, namely the number of pixels.
Since the pixels are addressed sequentially line by line, the number of lines that can be addressed is generally limited by the characteristics of the electro-optical effect of the liquid crystal used. The difference in voltages that can be achieved in direct addressing between an lit-up state and an off state, by placing the line and column voltages in phase or in phase opposition, diminishes with the number of lines. The possibility of addressing a large number of lines (<100) then arises to the detriment of the other characteristics of the panel (diminishing of contrast and an ever increasing variation in contrast with the visual angle). To improve the performance of these panels, a transistor or a non-linear element can be series connected with each pixel (forming a capacitor). The set then behaves like a memory element. A voltage is charged when the transistor is unblocked by a line pulse. This voltage is maintained in the pixel for the rest of the time of the frame during which the transistor is off.
At present, the requirements of display panel technology relate to a higher definition of the image. In matrix display type panels, this then leads to designing devices with a large number of addressing lines or columns. Their number can go up to 1024 or even more. This correspondingly increases the number of control transistors. For series manufacturing, it is necessary especially to obtain high output, good reproducibility and high stability for these components. It is further necessary to adapt, also with good reproducibility, the electrical characteristics of the component to that of the associated cell.
A presently common method of resolving this problem and of improving the performance of these panels consists in doing this addressing operation by means of a matrix of transistors in thin films: this amounts to directly coupling the electro-optical effect to a giant, but low-resolution "integrated circuit" responsible for performing the data shunting and memorizing functions.
This approach definitely entails technological difficulties both in the making of thin film transistors and as regards the interconnection conductors. In particular, it is imperative that, among the very large number of intersections between the lines and columns of the interconnection system, no intersection should be defective.
For, according to a usual technique, the transistors are located at the points of intersection of line conductors and column conductors which are insulated from each other in such a way that an appropriate potential difference, applied between a line and a column, determines whether the transistor connected between this line, this column and the adjacent pixel is on or off.
The present invention relates to display panels comprising a layer of electro-optical material controlled by an integrated matrix of transistors. This i
REFERENCES:
patent: 4470060 (1984-09-01), Yamazaki
patent: 4818077 (1989-04-01), Ohwada et al.
patent: 4820024 (1989-04-01), Nishiura
LaRoche Eugene R.
McCutcheon Nathan W.
Plottel Roland
Thomson Grand Public
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