Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Physical design processing
Reexamination Certificate
2007-08-01
2011-10-18
Chiang, Jack (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Integrated circuit design processing
Physical design processing
C716S106000, C716S111000
Reexamination Certificate
active
08042080
ABSTRACT:
An electro-migration verifying method is comprised of: a data inputting process step; a netlist updating process step (first process operation) for updating a netlist which is constructed by a wiring line parasitic element and a device element based upon a current density limit value database, a characteristic variation database, and wiring line current information; a current density calculating process step (second process operation) for calculating current density of the wiring line parasitic element from a device current and the updated netlist; a wiring line current information updating process step (third process operation) for updating the wiring line current information based upon the current density; a current density limit value comparing/judging process step (fourth process operation) for judging whether or not a current density value is located within the current density limit value based upon the updated wiring line current information and the current density limit value database; an electro-migration verifying process step constituted by the first process operation up to a fifth process operation of a step judging process step (fifth process operation) for judging a repetition process operation from step information; and a result outputting process step.
REFERENCES:
patent: 5878053 (1999-03-01), Koh et al.
patent: 6072945 (2000-06-01), Aji et al.
patent: 6308310 (2001-10-01), Nakamura
patent: 6675139 (2004-01-01), Jetton et al.
patent: 7210109 (2007-04-01), Caron et al.
patent: 7240314 (2007-07-01), Leung
patent: 7404161 (2008-07-01), Dutt et al.
patent: 7503021 (2009-03-01), Boucher et al.
patent: 2003/0014201 (2003-01-01), Schultz
patent: 2005/0289486 (2005-12-01), Caron et al.
patent: 2006/0015836 (2006-01-01), Curtin et al.
patent: 2006/0080630 (2006-04-01), Lin
patent: 2007/0299647 (2007-12-01), Bolcato et al.
patent: 2009/0024969 (2009-01-01), Chandra
patent: 11-175576 (1999-07-01), None
patent: 2001-352059 (2001-12-01), None
patent: 2002-009159 (2002-01-01), None
patent: 2002-175345 (2002-06-01), None
patent: 2003-188184 (2003-07-01), None
patent: 2005-251057 (2005-09-01), None
“HSIMplusPost-layout Analysis,” Synoposys Predictable Success, retrieved on May 31, 2007, Synopsys Inc., 2007.
“Astro-Rail, A Comprehensive Power-Integrity Analysis, Implementation and Verification Tool,” Synopsys Data Sheet, 2003.
Chiang Jack
McDermott Will & Emery LLP
Panasonic Corporation
Sandoval Patrick
LandOfFree
Electro-migration verifying apparatus, electro-migration... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Electro-migration verifying apparatus, electro-migration..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Electro-migration verifying apparatus, electro-migration... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4265752