Electrolysis: processes – compositions used therein – and methods – Electrolytic coating – Controlling current distribution within bath
Reexamination Certificate
1999-04-21
2001-07-17
Bell, Bruce F. (Department: 1741)
Electrolysis: processes, compositions used therein, and methods
Electrolytic coating
Controlling current distribution within bath
C205S103000, C205S123000, C205S128000, C205S149000, C205S153000, C205S157000, C204S297010, C204S297030, C204S230200, C204S230700, C204S260000, C204S261000, C204S263000, C204S272000, C204S273000, C204S275100
Reexamination Certificate
active
06261433
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to deposition of a metal layer onto a substrate. More particularly, the present invention relates to an apparatus and a method for electroplating a metal layer onto a substrate.
2. Background of the Related Art
Sub-micron multi-level metallization is one of the key technologies for the next generation of ultra large scale integration (ULSI). The multilevel interconnects that lie at the heart of this technology require planarization of interconnect features formed in high aspect ratio apertures, including contacts, vias, lines and other features. Reliable formation of these interconnect features is very important to the success of ULSI and to the continued effort to increase circuit density and quality on individual substrates and die.
As circuit densities increase, the widths of vias, contacts and other features, as well as the dielectric materials between them, decrease to sub-micron dimensions, whereas the thickness of the dielectric layers remains substantially constant, with the result that the aspect ratios for the features, i.e., their height divided by width, increases. Many traditional deposition processes have difficulty filling sub-micron structures where the aspect ratio exceed 2:1, and particularly where it exceeds 4:1. Therefore, there is a great amount of ongoing effort being directed at the formation of void-free, sub-micron features having high aspect ratios.
Elemental aluminum (Al) and its alloys have been the traditional metals used to form lines and plugs in semiconductor processing because of aluminum's low electrical resistivity, its superior adhesion to silicon dioxide (SiO
2
), its ease of patterning, and the ability to obtain it in a highly pure form. However, aluminum has a higher electrical resistivity than other more conductive metals such as copper and silver, and aluminum also can suffer from electromigration phenomena. Electromigration is considered as the motion of atoms of a metal conductor in response to the passage of high current density through it, and it is a phenomenon that occurs in a metal circuit while the circuit is in operation, as opposed to a failure occurring during fabrication. Electromigration can lead to the formation of voids in the conductor. A void may accumulate and/or grow to a size where the immediate cross-section of the conductor is insufficient to support the quantity of current passing through the conductor, and may also lead to an open circuit. The area of conductor available to conduct heat therealong likewise decreases where the void forms, increasing the risk of conductor failure. This problem is sometimes overcome by doping aluminum with copper and with tight texture or crystalline structure control of the material. However, electromigration in aluminum becomes increasingly problematic as the current density increases.
Copper and its alloys have lower resistivity than aluminum and higher electromigration resistance as compared to aluminum. These characteristics are important for supporting the higher current densities experienced at high levels of integration and increased device speed. Copper also has good thermal conductivity and is available in a highly pure state. Therefore, copper is becoming a choice metal for filling sub-micron, high aspect ratio interconnect features on semiconductor substrates.
Despite the desirability of using copper for semiconductor device fabrication, choices of fabrication methods for depositing copper into high aspect ratio features are limited. Precursors for CVD deposition of copper are ill-developed and involve complex and costly chemistry. Physical vapor deposition into such features produces unsatisfactory results because of limitations in ‘step coverage’ and voids formed in the features.
As a result of these process limitations, electroplating, which had previously been limited to the fabrication of patterns on circuit boards, is just now emerging as a method to fill vias and contacts on semiconductor devices.
FIGS. 1A-1E
illustrate a metallization technique for forming a dual damascene interconnect in a dielectric layer having dual damascene via and wire definitions, wherein the via has a floor exposing an underlying layer. Although a dual damascene structure is illustrated, this method can be applied also to metallize other interconnect features. The method generally comprises physical vapor depositing a barrier layer over the feature surfaces, physical vapor depositing a conductive metal seed layer, preferably copper, over the barrier layer, and then electroplating a conductive metal over the seed layer to fill the structure/feature. Finally, the deposited layers and the dielectric layers are planarized, such as by chemical mechanical polishing (CMP), to define a conductive interconnect feature.
Referring to
FIGS. 1A through 1E
, a cross sectional diagram of a layered structure
10
is shown including a dielectric layer
16
formed over an underlying layer
14
which contains electrically conducting features
15
. The underlying layer
14
may take the form of a doped silicon substrate or it may be a first or subsequent conducting layer formed on a substrate. The dielectric layer
16
is formed over the underlying layer
14
in accordance with procedures known in the art such as dielectric CVD to form a part of the overall integrated circuit. Once deposited, the dielectric layer
16
is patterned and etched to form a dual damascene via and wire definition, wherein the via has a floor
30
exposing a small portion of the conducting feature
15
. Etching of the dielectric layer
16
can be accomplished with various generally known dielectric etching processes, including plasma etching.
Referring to
FIG. 1A
, a cross-sectional diagram of a dual damascene via and wire definition formed in the dielectric layer
16
is shown. The via and wire definition facilitates the deposition of a conductive interconnect that will provide an electrical connection with the underlying conductive feature
15
. The definition provides vias
32
having via walls
34
and a floor
30
exposing at least a portion of the conductive feature
15
, and trenches
17
having trench walls
38
.
Referring to
FIG. 1B
, a barrier layer
20
of tantalum or tantalum nitride (TaN) is deposited on the via and wire definition, such that aperture
18
remains in the via
32
, by using reactive physical vapor deposition, i.e., by sputtering a tantalum target in a nitrogen/argon plasma. Preferably, where the aspect ratio of the aperture is high (e.g. 4:1 or higher) with a sub-micron wide via, the Ta/TaN is deposited in a high density plasma environment, wherein the sputtered deposition of the Ta/TaN is ionized and drawn perpendicularly to the substrate by a negative bias on the substrate. The barrier layer is preferably formed of tantalum or tantalum nitride, however other barrier layers such as titanium, titanium nitride and combinations thereof may also be used. The process used may be PVD, CVD, or combined CVD/PVD for texture and film property improvement. The barrier layer limits the diffusion of copper into the semiconductor substrate and the dielectric layer and thereby dramatically increases the reliability of the interconnect. It is preferred that the barrier layer has a thickness between about 25 Å and about 400 Å, most preferably about 100 Å.
Referring to
FIG. 1C
, a PVD copper seed layer
21
is deposited over the barrier layer
20
. Other metals, particularly noble metals, can also be used for the seed layer. The PVD copper seed layer
21
provides good adhesion for subsequently deposited metal layers, as well as a conformal layer for even growth of the copper thereover.
Referring to
FIG. 1D
, a copper layer
22
is electroplated over the PVD copper seed layer
21
to completely fill the via
32
with a copper plug
19
.
Referring to
FIG. 1E
, the top portion of the structure
10
, i.e., the exposed copper is then planarized, preferably by chemical mechanical polishing (CMP). Durin
Applied Materials Inc.
Bell Bruce F.
Thomason, Moser & Patterson L.L.P.
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