Electro-chemical deposition system

Details Electro-chemical deposition system Electro-chemical deposition system

2001-05-29

2003-10-21

Valentine, Donald R. (Department: 1742)

Chemistry: electrical and wave energy

Apparatus

Electrolytic

C204S212000, C204S22400M, C204S270000, C204S276000, C204S278000, C204S282000, C204S292000, C204S297030

Reexamination Certificate

active

06635157

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to deposition of a metal layer onto a wafer/substrate. More particularly, the present invention relates to an electro-chemical deposition or electroplating system for forming a metal layer on a wafer/substrate.
2. Background of the Related Art
Sub-quarter micron, multi-level metallization is one of the key technologies for the next generation of ultra large scale integration (ULSI). The multilevel interconnects that lie at the heart of this technology require planarization of interconnect features formed in high aspect ratio apertures, including contacts, vias, lines and other features. Reliable formation of these interconnect features is very important to the success of ULSI and to the continued effort to increase circuit density and quality on individual substrates and die.
As circuit densities increase, the widths of vias, contacts and other features, as well as the dielectric materials between them, decrease to less than 250 nanometers, whereas the thickness of the dielectric layers remains substantially constant, with the result that the aspect ratios for the features, i.e., their height divided by width, increases. Many traditional deposition processes, such as physical vapor deposition (PVD) and chemical vapor deposition (CVD), have difficulty filling structures where the aspect ratio exceed 4:1, and particularly where it exceeds 10:1. Therefore, there is a great amount of ongoing effort being directed at the formation of void-free, nanometer-sized features having high aspect ratios wherein the ratio of feature height to feature width can be 4:1or higher. Additionally, as the feature widths decrease, the device current remains constant or increases, which results in an increased current density in the feature.
Elemental aluminum (Al) and its alloys have been the traditional metals used to form lines and plugs in semiconductor processing because of aluminum's perceived low electrical resistivity, its superior adhesion to silicon dioxide (SiO
2
), its ease of patterning, and the ability to obtain it in a highly pure form. However, aluminum has a higher electrical resistivity than other more conductive metals such as copper, and aluminum also can suffer from electromigration leading to the formation of voids in the conductor.
Copper and its alloys have lower resistivities than aluminum and significantly higher electromigration resistance as compared to aluminum. These characteristics are important for supporting the higher current densities experienced at high levels of integration and increase device speed. Copper also has good thermal conductivity and is available in a highly pure state. Therefore, copper is becoming a choice metal for filling sub-quarter micron, high aspect ratio interconnect features on semiconductor substrates.
Despite the desirability of using copper for semiconductor device fabrication, choices of fabrication methods for depositing copper into very high aspect ratio features, such as a 4:1, having 0.35&mgr; (or less) wide vias are limited. As a result of these process limitations, plating, which had previously been limited to the fabrication of lines on circuit boards, is just now being used to fill vias and contacts on semiconductor devices.
Metal electroplating is generally known and can be achieved by a variety of techniques. A typical method generally comprises physical vapor depositing a barrier layer over the feature surfaces, physical vapor depositing a conductive metal seed layer, preferably copper, over the barrier layer, and then electroplating a conductive metal over the seed layer to fill the structure/feature. Finally, the deposited layers and the dielectric layers are planarized, such as by chemical mechanical polishing (CMP), to define a conductive interconnect feature.
FIG. 1
is a cross sectional view of a simplified typical fountain plater
10
incorporating contact pins. Generally, the fountain plater
10
includes an electrolyte container
12
having a top opening, a substrate holder
14
disposed above the electrolyte container
12
, an anode
16
disposed at a bottom portion of the electrolyte container
12
and a contact ring
20
contacting the substrate
22
. A plurality of grooves
24
are formed in the lower surface of the substrate holder
14
. A vacuum pump (not shown) is coupled to the substrate holder
14
and communicates with the grooves
24
to create a vacuum condition capable of securing the substrate
22
to the substrate holder
14
during processing. The contact ring
20
comprises a plurality of metallic or semi-metallic contact pins
26
distributed about the peripheral portion of the substrate
22
to define a central substrate plating surface. The plurality of contact pins
26
extend radially inwardly over a narrow perimeter portion of the substrate
22
and contact a conductive seed layer of the substrate
22
at the tips of the contact pins
26
. A power supply (not shown) is attached to the pins
26
thereby providing an electrical bias to the substrate
22
. The substrate
22
is positioned above the cylindrical electrolyte container
12
and electrolyte flow impinges perpendicularly on the substrate plating surface during operation of the cell
10
.
While present day electroplating cells, such as the one shown in
FIG. 1
, achieve acceptable results on larger scale substrates, a number of obstacles impair consistent reliable electroplating onto substrates having micron-sized, high aspect ratio features. Generally, these obstacles include providing uniform power distribution and current density across the substrate plating surface to form a metal layer having uniform thickness, preventing unwanted edge and backside deposition to control contamination to the substrate being processed as well as subsequent substrates, and maintaining a vacuum condition which secures the substrate to the substrate holder during processing. Also, the present day electroplating cells have not provided satisfactory throughput to meet the demands of other processing systems and are not designed with a flexible architecture that is expandable to accommodate future designs rules and gap fill requirements. Furthermore, current electroplating system platforms have not provided post electrochemical deposition treatment, such as a rapid thermal anneal treatment, for enhancing deposition results within the same system platform.
Additionally, current electroplating systems are incapable of performing necessary processing steps without resorting to peripheral components and time intensive efforts. For example, analysis of the processing chemicals is required periodically during the plating process. The analysis determines the composition of the electrolyte to ensure proper proportions of the ingredients. Conventional analysis is performed by extracting a sample of electrolyte from a test port and transferring the sample to a remote analyzer. The electrolyte composition is then manually adjusted according to the results of the analysis. The analysis must be performed frequently because the concentrations of the various chemicals are in constant flux. However, the foregoing method is time consuming and limits the number of analyses which can be performed.
Therefore, there remains a need for an electro-chemical deposition system that is designed with a flexible architecture that is expandable to accommodate future designs rules and gap fill requirements and provides satisfactory throughput to meet the demands of other processing systems. There is also a need for an electro-chemical deposition system that provides uniform power distribution and current density across the substrate plating surface to form a metal layer having uniform thickness and maintain a vacuum condition which secures the substrate to the substrate holder during processing. It would be desirable for the system to prevent and/or remove unwanted edge and backside deposition to control contamination to the substrate being processed as well as subsequent substrates. It would

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