Electrolysis: processes – compositions used therein – and methods – Electrolytic coating – Coating moving substrate
Reexamination Certificate
1999-04-19
2002-07-09
Valentine, Donald R. (Department: 1741)
Electrolysis: processes, compositions used therein, and methods
Electrolytic coating
Coating moving substrate
C204S275100, C204S22400M, C204S297010, C204S282000, C204S284000, C204S222000, C204S212000, C204S278000, C204S297030
Reexamination Certificate
active
06416647
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to deposition of a metal layer onto a substrate. More particularly, the present invention relates to electroplating a metal layer onto a substrate.
2. Background of the Related Art
Sub-quarter micron multi-level metallization is one of the key technologies for the next generation of ultra large scale integration (ULSI). The multilevel interconnects that lie at the heart of this technology require planarization of interconnect features formed in high aspect ratio apertures, including contacts, vias, lines and other features. Reliable formation of these interconnect features is very important to the success of ULSI and to the continued effort to increase circuit density and quality on individual substrates and die.
As circuit densities increase, the widths of vias, contacts and other features, as well as the dielectric materials between them, decrease to less than 250 nanometers, whereas the thickness of the dielectric layers remains substantially constant, with the result that the aspect ratios for the features, i.e., their height divided by width, increases. Many traditional deposition processes have difficulty filling structures where the aspect ratio exceed 4:1, and particularly where it exceeds 10:1. Therefore, there is a great amount of ongoing effort being directed at the formation of void-free, nanometer-sized features having high aspect ratios wherein the ratio of feature height to feature width can be 4:1 or higher. Additionally, as the feature widths decrease, the device current remains constant or increases, which results in an increased current density in the feature.
Elemental aluminum (Al) and its alloys have been the traditional metals used to form lines and plugs in semiconductor processing because of aluminum's perceived low electrical resistivity, its superior adhesion to silicon dioxide (SiO
2
), its ease of patterning, and the ability to obtain it in a highly pure form. However, aluminum has a higher electrical resistivity than other more conductive metals such as copper, and aluminum also can suffer from electromigration phenomena. Electromigration is believed to be the motion of ions of a metal conductor in response to the passage of high current through it, and it is a phenomenon that occurs in a metal circuit while the circuit is in operation, as opposed to a failure occurring during fabrication. Electromigration can lead to the formation of voids in the conductor. A void may accumulate and/or grow to a size where the immediate cross-section of the conductor is insufficient to support the quantity of current passing through the conductor, leading to an open circuit. The area of conductor available to conduct heat therealong likewise decreases where the void forms, increasing the risk of conductor failure. This problem is sometimes overcome by doping aluminum with copper and with tight texture or crystaline structure control of the material. However, electromigration in aluminum becomes increasingly problematic as the current density increases.
Copper and its alloys have lower resistivities than aluminum and significantly higher electromigration resistance as compared to aluminum. These characteristics are important for supporting the higher current densities experienced at high levels of integration and increase device speed. Copper also has good thermal conductivity and is available in a highly pure state. Therefore, copper is becoming a choice metal for filling sub-quarter micron, high aspect ratio interconnect features on semiconductor substrates.
Despite the desirability of using copper for semiconductor device fabrication, choices of fabrication methods for depositing copper into very high aspect ratio features, such as a 10:1 aspect ratio, 0.1&mgr; wide vias are limited. Precursors for CVD deposition of copper are ill-developed, and physical vapor deposition into such features produces unsatisfactory results because of voids formed in the features.
As a result of these process limitations, plating which had previously been limited to the fabrication of lines on circuit boards, is just now being used to fill vias and contacts on semiconductor devices. Metal electroplating in general is well known in the art and can be achieved by a variety of techniques. However, a number of obstacles impair consistent reliable electroplating of copper onto semiconductor substrates having nanometer-sized, high aspect ratio features. Generally, these obstacles deal with providing uniform power distribution and current density across the substrate plating surface to form a metal layer having uniform thickness.
Present designs of cells for electroplating a metal on semiconductor substrates are based on a fountain plater configuration.
FIG. 1
is a cross sectional view of a simplified fountain plater. Generally, the fountain plater
10
includes an electrolyte container
12
having a top opening, a substrate holder
14
disposed above the electrolyte container
12
, an anode
16
disposed at a bottom portion of the electrolyte container
12
and a cathode
20
contacting the substrate
18
. The cathode
20
comprises a plurality of contact pins distributed about the peripheral portion of the substrate
18
to provide a bias about the perimeter of the substrate. The contact pins generally provide a higher current density near the contact points on the substrate surface, resulting in a non-uniform deposition on the substrate surface. The semiconductor substrate
18
is positioned a fixed distance above the cylindrical electrolyte container
12
, and the electrolyte impinges perpendicularly on the substrate plating surface. Because of the dispersion effects of the electrical current at the exposed edges of the substrate
18
and the non-uniform flow of the electrolyte, the fountain plater
10
provides non-uniform current distribution, particularly at the region near the edges and at the center of the substrate
18
that results in non-uniform plating of the metal. The electrolyte flow uniformity at the center of the substrate
18
can be improved by rotating the substrate
18
. However, the plating uniformity still deteriorates as the boundaries or edges of the substrate are approached.
Furthermore, the fountain plater
10
presents additional difficulties in substrate transfers because the substrate has to be flipped for face-down plating. Generally, substrates are transferred by robots having robot blades with a substrate supporting surface, and the substrates are transferred with the surface to be processed face-up. Preferably, the robot blade does not contact the surface to be processed to eliminate risk of damaging the substrate surface. Because the fountain plater
10
requires face-down processing, additional devices are required to flip the substrate from a face-up transferring position to a face-down processing position.
Therefore, there remains a need for a reliable, consistent copper electroplating technique to deposit and form copper layers on semiconductor substrates having nanometer-sized, high aspect ratio features. There is also a need for a face-up electroplating system that allows fast substrate processing and increases throughput. Furthermore, there is a need for an apparatus for delivering a uniform electrical power distribution to a substrate surface and a need for an electroplating system that provides uniform deposition on the substrate surface.
SUMMARY OF THE INVENTION
The invention generally provides an apparatus and a method for electro-chemically depositing a uniform metal layer onto a substrate. More specifically, the invention provides an electro-chemical deposition cell for face-up processing of semiconductor substrates comprising a substrate support member, a cathode connected to the substrate plating surface, an anode disposed above the substrate support member and an electroplating solution inlet supplying an electroplating solution fluidly connecting the anode and the substrate plating surface. Preferably, the anode comprises a consumable
Denome Mark
Dordi Yezdi
Edwards Roy
Lowrance Bob
Stevens Joe
Applied Materials Inc.
Thomason Moser & Patterson LLP
Tran Thao
Valentine Donald R.
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