Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-12-20
2004-04-27
Zaribian, Amir (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S336000, C257S344000, C257S408000
Reexamination Certificate
active
06727534
ABSTRACT:
TECHNICAL FIELD
The present invention relates to the field of metal oxide semiconductor (MOS) transistors, and more particularly, to MOS transistors with electrically programmed source/drain series resistance.
BACKGROUND OF THE INVENTION
An important aim of ongoing research in the semiconductor industry is increasing the performance of semiconductor devices. Planar transistors, such as metal oxide semiconductor field effect transistors (MOSFET) are particularly well suited for use in high-density integrated circuits. There are two general types of MOS transistors, N-channel MOS (NMOS) formed with n-type source and drain regions in a p-type wafer, and P-channel MOS (PMOS) formed with p-type source and drain regions. NMOS transistors conduct electrons through the transistor channel, while PMOS transistors conduct holes through the transistor channel. Typically, the source and drain regions are doped with phosphorous or arsenic to form n-type source/drain regions, while boron doping is used to form p-type source/drain regions.
Complementary metal oxide semiconductor (CMOS) devices comprise N- and P-channel MOS transistors on the same substrate. It is desirable to improve CMOS device speed to produce high-performance semiconductor devices. Reducing the electrical resistance of the source/drain regions increases the speed of a transistor. It is desirable to produce high-speed transistor devices in an efficient manner using conventional materials for forming CMOS transistors.
The term semiconductor devices, as used herein, is not to be limited to the specifically disclosed embodiments. Semiconductor devices, as used herein, include a wide variety of electronic devices including flip chips, flip chip/package assemblies, transistors, capacitors, microprocessors, random access memories, etc. In general, semiconductor devices refer to any electrical device comprising a semiconductor.
SUMMARY OF THE INVENTION
There exists a need in the semiconductor device art to provide a high-speed MOSFET. There exists a need in this art to provide high-speed CMOS devices formed from conventional transistor materials. There exists a need in this art to provide CMOS devices with reduced series resistance source/drain regions.
These and other needs are met by embodiments of the present invention, which provide a semiconductor device comprising a semiconductor substrate with a transistor formed thereon. The transistor comprises a gate electrode with opposing sidewalls formed on the substrate. An active region is formed in the substrate. Insulating sidewall spacers are formed alongside and in contact with the gate electrode opposing sidewalls. A conductive layer is embedded in the sidewall spacers. The embedded conductive layer is electrically insulated from the gate electrode and the active region.
The earlier stated needs are also met by certain embodiments of the present invention which provide a method of forming a semiconductor device comprising providing a semiconductor substrate with a transistor formed thereon. The transistor comprises a gate electrode with opposing sidewalls formed on the substrate and an active region formed in the substrate. A first insulating layer is formed over the gate electrode and active region, and a conductive layer is deposited over the first insulating layer. Portions of the conductive layer are removed to expose portions of the first insulating layer overlying the gate electrode and active region. A second insulating layer is formed over the conductive layer and first insulating layer. Portions of the first insulating layer and the second insulating layer are removed to form sidewall spacers, alongside and in contact with the gate electrode opposing sidewalls, with the conductive layer embedded therein.
This invention addresses the need for improved high-speed transistors, such as CMOS devices. This invention addresses the need for transistors with electrically programmed, reduced series resistance source/drain regions.
The foregoing and other features, aspects, and advantages of the present invention will become apparent in the following detailed description of the present invention when taken in conjunction with the accompanying drawings.
REFERENCES:
patent: 5234852 (1993-08-01), Liou
patent: 5541434 (1996-07-01), Nicholls et al.
patent: 5621236 (1997-04-01), Choi et al.
patent: 5726081 (1998-03-01), Lin et al.
patent: 5793089 (1998-08-01), Fulford et al.
patent: 5808347 (1998-09-01), Kurimoto et al.
patent: 6001697 (1999-12-01), Chang et al.
patent: 6043545 (2000-03-01), Tseng et al.
patent: 6150276 (2000-11-01), Lee et al.
patent: 6180490 (2001-01-01), Vassiliev et al.
patent: 6207530 (2001-03-01), Hsu et al.
patent: 6300172 (2001-10-01), Ang et al.
patent: 6306701 (2001-10-01), Yeh
patent: 6399451 (2002-06-01), Lim et al.
patent: 6461951 (2002-10-01), Besser et al.
patent: 6483154 (2002-11-01), Ngo et al.
patent: 6507123 (2003-01-01), Woo et al.
patent: 6512273 (2003-01-01), Krivokapic et al.
patent: 2001/0016383 (2001-08-01), Chen et al.
patent: 2002/0163036 (2002-11-01), Miura et al.
patent: 2002/0182813 (2002-12-01), Ahmed et al.
patent: 2003/0107071 (2003-06-01), Terauchi et al.
“Condensed Chemical Dictionary”, 2001, p. 992.
Peter Van Zant, “Microchip Fabrication, A Practical Guide to Semiconductor Processing” 4 ed, 1997, pp. 404-405 (2000).
<www.accuratus.com.silinit.html>Apr. 24, 2003, pp. 1-3.
<www.cerac.com/pubs/prodadata/ta205.htm>Apr. 24, 2003, pp. 1-4.
IME Strategic Focuses Deep Submicron Shallow Trench Isolation Module Development.
Surface Interface “Stylus NanoProfilometer (SNP)” SNP 9000 Applications.
Buller James F.
Wristers Derick J.
Xiang Qi
Advanced Micro Devices , Inc.
Soward Ida M.
Zaribian Amir
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