Active solid-state devices (e.g. – transistors – solid-state diode – Test or calibration structure
Reexamination Certificate
2003-07-08
2004-11-02
Ngô, Ngân V. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Test or calibration structure
C257S368000, C257S401000
Reexamination Certificate
active
06812488
ABSTRACT:
BACKGROUND
1. Technical Field of the Invention
The present invention relates to the field of integrated circuits, and more particularly to electrically programmable three-dimensional (3-D) memory-based IC self-test.
2. Related Arts
In a three-dimensional (3-D) integrated circuit (3D-IC), one or more 3D-IC layers are stacked one above another on top of a substrate. Each IC layer comprises functional blocks such as logic, memory and analog blocks. It is typically comprised of non-single-crystalline (poly, microcrystalline or amorphous) semiconductor material. Because logic and analog blocks are sensitive to defects and non-single-crystalline semiconductor material has a large defect density, the 3D-IC comprising logic and/or analog blocks have a low yield. Moreover, logic and/or analog blocks consume large power. The three-dimension integration of these blocks faces many heat-dissipation issues. On the other hand, a memory block is less sensitive to defects because the defect-induced errors can be corrected (by, for example, redundancy circuit). Moreover, it consumes little power. Accordingly, memory is better suited for the 3-D integration.
In a three-dimensional memory (3D-M), one or more memory levels are stacked one above another on top of a substrate. As illustrated in
FIG. 1
, the two physical memory levels
100
,
200
of the 3D-M
0
are stacked one by one on a substrate
0
s
. On each memory level
100
, there are a plurality of address-select lines (including word line
20
a
and bit line
30
a
) and 3D-M cells (
1
aa
. . . ). Substrate
0
s
comprises a plurality of transistors. Contact vias (
20
av
,
30
av
. . . ) provide electrical connection between address-select lines (
20
a
,
30
a
. . . ) and the substrate circuit.
The 3D-M can be categorized through the means employed to alter its contents. If the contents can be altered using electrical means, this 3D-M is an electrically programmable 3D-M (EP-3DM); if the contents are altered using non-electrical means, then this 3D-M is a non-electrically programmable 3D-M (NEP-3DM).
The electrically programmable 3D-M (EP-3DM) can be further categorized into 3-D RAM (3D-RAM), 3-D write-once memory (a.k.a. 3-D one-time programmable, i.e. 3D-OTP), and 3-D write-many (3D-WM). The 3D-RAM cell is similar to a conventional RAM cell except that the transistors used therein are thin-film transistors (TFT)
1
t
(FIG.
1
B). The 3D-OTP cell may comprise a 3D-ROM layer
22
(e.g. a diode layer) and an antifuse layer
22
a
(FIG.
1
C). The integrity of the antifuse layer
22
a
indicates the logic state of the 3D-OTP cell. The 3D-WM includes 3D-flash, 3D-MRAM (3-D magneto-resistive-material-based RAM), 3D-FRAM (3-D Ferroelectric-material-based RAM), 3D-OUM (3-D Ovonyx-unified-memory), etc. It may comprise active devices such as TFT
1
t
(FIGS.
1
DA-
1
DB). The TFT-based 3D-WM may comprise a floating gate
30
fg
(FIG.
1
DA) or a vertical channel
25
c
(FIG.
1
DB).
An exemplary non-electrically programmable 3D-M (NEP-3DM) is mask-programmable 3-D read-only memory (3D-MPROM). It represents logic “1” with the existence of an info-via
24
(i.e. absence of dielectric
26
) (FIG.
1
EA); and logic “0” with the absence of an info-via (i.e. existence of dielectric
26
) (FIG.
1
EB). Similar to 3D-OTP cell (FIG.
1
C), it also comprises a 3D-ROM layer
22
(e.g. a diode layer).
3D-M can also be categorized as conventional semiconductor memory, i.e. it can be categorized into 3D-RAM and 3D-ROM (including 3D-MPROM, 3D-OTP, 3D-WM). This is the approach used by prior patents and patent applications filed by the same inventor (U.S. Pat. No. 5,835,396, U.S. patent application Ser. No. 10/230,648, etc.) In this application, both categorizations are used interchangeably.
With low-cost, high density and large bandwidth, the 3D-M has a strong competitive edge. However, because it is typically based on non-single-crystalline semiconductor, the performance of the 3D-M cell cannot yet compete with the conventional memory. For the 3D-M designed and manufactured in conventional approaches, its performance, such as read-write speed, unit-array capacity, intrinsic yield and programmability, needs further improvement.
The present invention provides an improved three-dimensional memory (3D-M). It has better integratibility, speed, density/cost and programmability. The 3D-M can be used to form three-dimensional integrated memory (3DiM), e.g. computer-on-a-chip (ConC) and player-on-a-chip (PonC). ConC/PonC offers excellent data security. Another 3D-M application of great importance is in the area of the integrated-circuit (IC) testing. 3D-M carrying the IC test data can be integrated with the circuit-under-test (CUT), thus enabling at-speed test and self-test.
It should be noted that, although various types of the 3D-M (including both EP-3DM- and NEP-3DM) are described hereinafter, the scope of this Application is limited to the EP-3DM only. The NEP-3DM is expressly excluded from the scope of this Application.
OBJECTS AND ADVANTAGES
It is a principle object of the present invention to provide an integrated circuit (IC) with self-test and at-speed test capabilities.
It is a further object of the present invention to provide an IC self-test based on electrically programmable three-dimensional memory (EP-3DM).
It is a further object of the present invention to provide an IC self-test method with minimum impact to the layout of the circuit-under-test.
In accordance with these and other objects of the present invention, an EP-3DM-based IC self-test is disclosed.
SUMMARY OF THE INVENTION
Compared with conventional memory, one greatest advantage of the 3D-M is its integratibility. Because its memory cells do not occupy substrate, most substrate real estate can be used to build complex substrate integrated circuits (substrate-IC). The substrate-IC may comprise conventional memory block, processing unit, analog block and others. 3D-M SoC (system-on-a-chip) formed from the integration between the 3D-M and substrate-IC is referred in the present invention as three-dimensional integrated memory (3DiM). The 3DiM can further improve the data security, speed, yield and software upgradibility of the 3D-M.
In a 3DiM, the substrate-IC may comprise an embedded read-write memory (eRWM) and/or an embedded processor (eP). The performance of the 3D-M and the eRWM are complementary to each other: 3D-M excels in integratibility and density/cost; RWM is better in speed and programmability. The integration of the 3D-M and the RWM combines their individual strength and can achieve an optimized system performance. On the other hand, the integration of the 3D-M and the eP can enable the on-chip processing of the 3D-M data (data stored in the 3D-M), thus improving the 3D-M data security.
One exemplary eRWM is embedded RAM (eRAM). The eRAM has a small latency. It can be used as a cache for the 3D-M data, i.e. it keeps a copy of the 3D-M data. When the eP seeks data, it searches first in the eRAM. If not found, it will then search the 3D-M. This approach reconciles the speed difference between the eP and the 3D-M. Another exemplary eRWM is embedded ROM (eROM). In general, eROM comprises non-volatile memory (NVM). The excellent programmability of the eROM can remedy the limited programmability of the 3D-M. Accordingly, the eROM is an ideal storage device for the correctional data (data used to correct defect-induced errors) and upgrade code of the 3D-M.
Computer-on-a-chip (ConC) is realized by integrating a 3D-M with an eP and an eRWM. It can perform many task of a today's computer. One exemplary ConC is player-on-a-chip (PonC). PonC can store and play contents, including audio/video (A/V) materials, electronic books, electronic maps and others. It provides excellent copyright protection to these contents. For the conventional content-storage technologies such as optical discs, pirates can easily steal the original contents by monitoring the output signal from the content carrier (i.e. the medium that carries the content, including optical discs ROM chips and others) or by rever
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