Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
1999-03-17
2001-01-23
Dinh, Son T. (Department: 2824)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185180, C365S185190
Reexamination Certificate
active
06178118
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor memory devices and, more particularly, to electrically programmable memory devices with improved programmability.
2. Description of the Related Art
Electronically programmable read only memory (EPROM), erasable electronically programmable read only memory (EEPROM) and Flash memory are classes of floating gate memory devices. More particularly, these floating gate memory devices are programmable memory devices which use floating gates as charge storage layers.
In recent years, techniques have been developed to increase the programming speed for floating gate memories. In particular, U.S. Pat. No. 5,615,153 describes an approach to increase programming speed by increasing wordline (gate voltages) while source voltage is held constant, and is hereby incorporated by reference. By starting at a lower wordline voltage, and increasing the wordline voltage to a higher wordline voltage during programming, programming speed is increased and a high final turn-on threshold voltage can be achieved.
While this approach is able to increase programming speed, there are still several disadvantages. One disadvantage is that threshold voltage distribution difficulties can result when fast programming is performed. Another disadvantage is that programming of floating gate memories has been done in small programming steps wherein after the completion of each programming step a verifying operation must be performed to determine the validity of the last programming step. The verifying operation has typically been done as a separate operation. For example, such repetitive programming techniques are further described in U.S. Pat. No. 5,172,338 and U.S. Pat. No. 5,220,531. As a result, these conventional repetitive programming techniques require a long time for programming to complete largely because of the inefficiency of having to switch between a programming mode of operation and a verify mode of operation after each programming step.
In the view of the foregoing, there is a need for faster and more efficient schemes for programming electrically programmable memory cells.
SUMMARY OF THE INVENTION
Broadly speaking, the invention pertains to an electronically programmable semiconductor memory device that is able to provide stepped wordline voltages during programming of multi-level threshold voltages into memory cells within the electronically programmable semiconductor memory device. The stepping through the wordline voltages is controlled by source-side voltage monitoring of the memory cells during programming.
The invention can be implemented in numerous ways, including as a device, an apparatus and a method. Several embodiments of the invention are discussed below.
As a semiconductor memory device, one embodiment of the invention includes: an array of floating gate memory cells, the array including wordlines, bitlines and ground lines, each of the floating gate memory cells can be programmed to three or more different threshold voltage levels; a program controller operatively connected to at least one of the bitlines of the array, the program controller to receive data to be stored in the array and to control the programming of the threshold voltage levels in the floating gate memory cells in accordance with the received data; and a wordline program voltage controller operatively connected to at least one of the wordlines of the array, the wordline program voltage controller provides a stepped wordline voltage to the at least one of the wordlines of the array dependent on upon the threshold voltage level to be programmed.
As a semiconductor memory device, another embodiment of the invention includes: an array of floating gate memory cells, the array including wordlines, bitlines and ground lines, each of the floating gate memory cells can be programmed to three or more different threshold voltage levels; a program controller operatively connected to at least one of the bitlines of the array, the program controller to receive data to be stored in the array and to control the programming of the threshold voltage levels in the floating gate memory cells in accordance with the received data; a program current controller that resistively couples at least one of the ground lines of the array to a predetermined low voltage potential during programming of the threshold voltages; and a wordline program voltage controller operatively connected to at least one of the wordlines of the array, the wordline program voltage controller provides a stepped wordline voltage to the at least one of the wordlines of the array dependent on a signal level on the at least one of the ground lines of the array.
As a method for programming a threshold voltage level in a memory cell of an electricially programmable semiconductor memory device to one of a plurality of predetermined threshold voltage levels, one embodiment of the invention includes the operations of: applying a high voltage to a drain terminal of the memory cell; applying a first gate voltage to a gate terminal of the memory cell during a first programming phase when a first threshold voltage level is being programmed; coupling a source terminal of the memory cell to a low voltage; monitoring the voltage on the source terminal of the memory cell during the programming to determine when the first threshold voltage level has been programmed; and subsequently applying a second gate voltage to the gate terminal of the memory cell during a second programming phase after the monitoring determines that the first threshold voltage level has been programmed and when a second threshold voltage level is being programmed, the second gate voltage being greater than the first gate voltage.
The invention has numerous advantages. Different implementations or embodiments of the invention may have one or more of the following advantages. One advantage is that memory cells are able to be programmed at high speed with good self-convergence and improved threshold voltage distribution can be obtained. Another advantage of the invention is that verification can be simultaneously performed with the programming of memory cells in the semiconductor memory device.
Other aspects and advantages of the invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.
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Lin Chin-Hsi
Ni Ful-Long
Beyer Weaver & Thomas LLP
Dinh Son T.
Macronix International Co. Ltd.
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