Electrically programmable read-only memory cell

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

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257316, 257239, H01C 29788, H01C 27148

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active

056169418

ABSTRACT:
A floating gate (51)is formed to have a cavity (52) that increases the capacitive coupling between the floating gate (51) and a control gate for the memory cell. The memory cell may be used in EPROM, EEPROM, and flash EEPROM arrays and may be programmed and erased by hot carrier injection, Fowler-Nordheim tunneling or the like. The process sequence for forming the cavity (52) of the floating gate (51) has good process margin allowing some lithographic misalignment. In one embodiment, a multi-tiered floating gate may be formed. The multi-tier structure allows the capacitive coupling to further increase without occupying more area.

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Taguchi, et al.; "A 40-ns 64-Mb DRAM with 64-b Parallel Data Bus Architecture;" IEEE Jour. of Solid-State Circuits; vol. 26, No. 11, pp. 1493-1497 (1991).
Itabashi, et al.; "A Split Wordline Cell For 16Mb SRAM Using Polysilicon Sidewall Contacts;" IEDM; pp. 477-480 (1991).
Kume, et al.; "A 1.28.mu.m2 Contactless Memory Cell Technology for a 3V-Only 64Mbit EEPROM;" 1992 IEDM Tech. Dig.; CH.3211-0, pp. 91-93 (Dec. 1992).

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