Static information storage and retrieval – Read/write circuit – Testing
Patent
1981-12-23
1985-09-24
Popek, Joseph A.
Static information storage and retrieval
Read/write circuit
Testing
365226, 365230, G11C 1140
Patent
active
045436479
ABSTRACT:
An electrically programmable non-volatile semiconductor memory device includes a plurality of word lines; a plurality of bit lines; and cell transistors, each having a control gate connected to the word line, a drain connected to the bit line, and a floating region for storing electrical charges therein are arranged at cross points of the word lines and the bit lines. An information "0" is written in the cell at the cross point by applying a high electric potential to both the selected word line and the selected bit line, and an information "1" is written in the cell by applying a high electric voltage to the word line and a low voltage to the bit line. For the purpose of testing whether or not the cell transistor is good, one control circuit or a plurality of additional control circuits can be used to simultaneously place all word lines and/or all bit lines in a selected state or in non-selected state.
REFERENCES:
patent: 3795898 (1974-03-01), Mehta et al.
patent: 3969706 (1976-07-01), Proebsting et al.
patent: 4094012 (1978-06-01), Perlegos et al.
patent: 4336603 (1982-06-01), Kotecha et al.
patent: 4342103 (1982-07-01), Higuchi et al.
Fujitsu Limited
Popek Joseph A.
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