Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-09-20
2001-04-10
Wojciechowicz, Edward (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S298000, C257S302000, C257S314000, C257S321000, C257S328000, C257S330000, C438S156000, C438S243000, C438S253000, C438S259000, C438S300000, C438S542000, C438S644000
Reexamination Certificate
active
06215140
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention lies in the semiconductor technology field. More specifically, the invention relates to an electrically programmable, non-volatile memory cell configuration having a semiconductor substrate of a first conductivity type,
in which at least one first address line and at least one second address line are provided and the second address line crosses the first address line with a space between them;
in which a memory cell is located essentially between the first address line and the second address line, is arranged at least partially in the semiconductor substrate and has, there, at least one first doped region of the second conductivity type forming a direct junction between the two conductivity types, in which case this junction allows an electrical current flow between the first address line and the second address line in the semiconductor substrate to be limited unidirectionally; and
in which at least one intermediate layer, which is part of the memory cell, is located on the semiconductor substrate between the first address line and the second address line.
The invention further pertains to a method of producing such a memory cell configuration.
A large number of different memories are used for data processing. For example, a computer contains both a read only memory ROM as well as a dynamic memory (Dynamic Random Access Memory) DRAM. DRAMs are so-called volatile memories, in which the stored information must be refreshed regularly. In contrast to this, data refreshing is not necessary in so-called read only memories (ROMs), since the data are stored permanently. Normally, data are stored in a read only memory during its production process. However, in contrast, programmable read only memories are more advantageous, in the case of which a suitable programming technique is used to write the information to these read only memories only after they have been produced. Such read only memories are also referred to as Programmable Read Only Memories (PROMs).
A programmable read only memory is described, for example, in U.S. Pat. No. 5,536,968 to Crafts et al. The essence of that read only memory is a diode matrix in which each matrix element comprises a diode and a thermal resistance element, and is connected to in each case one data input line and one data output line. The resistance elements, which are of relatively complex design, occupy a large amount of space and produce the connection between the data input lines and data output lines via the diodes, can be caused to melt by a current surge. This results in the electrical connection within a matrix element being interrupted, and thus in information being stored there. When the resistance element is intact, the matrix element represents, for example, a logic 1, while, in contrast, when the resistance element has been melted, it represents a logic 0. This information can subsequently be interrogated by checking the individual matrix elements.
A memory cell of the type mentioned initially is disclosed, for example, in U.S. Pat. No. 4,677,742 to Johnson. In that memory cell configuration, first address lines and second address lines which each run parallel to one another are arranged on a semiconductor substrate. The first address lines and second address lines cross, with a space between them formed by the semiconductor substrate. A so-called PIN diode has in each case been formed, by successive deposition of a plurality of semiconductor layers, at the intersections between the first address lines and second address lines. Furthermore, a layer whose resistance value can be changed once is located between each diode and each address line, whose resistance value governs the memory content of each individual memory cell located in the intersection area of the address lines. The space requirement for this memory cell configuration is, disadvantageously, relatively high. If, for example, the smallest technologically achievable structure width is denoted by F, then a memory cell in the memory cell configuration described by Johnson requires an area of 4 F
2
.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a memory cell configuration, which overcomes the above-mentioned disadvantages of the heretofore-known devices and methods of this general type and the individual memory cells of which require only a small amount of space.
With the foregoing and other objects in view there is provided, in accordance with the invention, an electrically programmable, non-volatile memory cell configuration in a semiconductor substrate of a first conductivity type. The configuration comprises:
a trench with at least one side wall is formed in the semiconductor substrate;
at least one first address line running along the side wall of the trench in the substrate, and at least one second address line in the substrate crossing the first address line at a spaced distance therefrom;
a memory cell substantially between the first address line and the second address line at least partially in the semiconductor substrate, the memory cell having at least one first doped region of a second conductivity type forming a direct junction between the first and second conductivity types, the direct junction allowing an electrical current flow between the first address line and the second address line in the semiconductor substrate to be limited unidirectionally; and
at least one intermediate layer on the semiconductor substrate between the first address line and the second address line forming a part of the memory cell.
According to the invention, the first address line is routed along a side wall of the trench. This opens up the possibility of producing memory cells which require less space. The first address line arranged on the side wall may be designed to be relatively thin, seen in cross section, but nevertheless broad, that is to say extending relatively far into the depth of the trench, without resulting in any additional space requirement. The trench need only be designed to be deep enough for this purpose. It is advantageous in this case that the relatively broad first address line has a low electrical resistance, even with a small structure width F, owing to its relatively large cross-sectional area.
It is furthermore advantageous that a first address line can be arranged, for example, on each of the opposite side walls of the trench, so that two first address lines are accommodated in a trench having a structure width of 1 F, at the same time. This reduces the space requirement for an individual memory cell at least to 2 F
2
. If, for example, a technologically achievable structure width F of 0.18 &mgr;m is assumed, then the necessary space requirement is only 0.0648 &mgr;m
2
. Roughly 15 bits can thus be stored per &mgr;m
2
.
The first address line is preferably composed of a semiconductor material which is doped by a dopant of the second conductivity type. It has been found to be advantageous to produce the first address line from in-situ-doped polysilicon having a dopant content of between 10
20
/cm
3
to 10
22
/cm
3
. Arsenic or phosphorus may be used, for example, as dopants for n-doping. The first address lines may also, of course, be p-doped. The semiconductor substrate is then n-conductive.
The high dopant content on the one hand ensures that the polysilicon conductivity is high, as a result of which the first address line may be designed in a particularly space-saving manner. On the other hand, the high dopant content of the first address line provides a large reservoir of dopants, which contributes to the formation of the first doped region of the second conductivity type. The dopants contained in the first address line diffuse, for example activated by a thermal process, to a certain extent into the semiconductor substrate of the first conductivity type, where they form the first doped region. This results in a direct junction between the two conductivity types being formed in the semiconductor substrate, limiting the current flow through this junction uni
Franosch Martin
Lange Gerrit
Lehmann Volker
Reisinger Hans
Schafer Herbert
Greenberg Laurence A.
Lerner Herbert L.
Siemens Aktiengesellschaft
Stemer Werner H.
Wojciechowicz Edward
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