Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-08-25
2003-10-28
Booth, Richard (Department: 2812)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S321000, C438S259000
Reexamination Certificate
active
06639269
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to an electrically programmable memory cell configuration and a method for fabricating it.
In semiconductor-based electrically programmable memories, so-called EEPROMs, information is stored in the form of at least two different threshold voltages of transistors. In order to read out an item of information of one of the transistors, a voltage lying between the two threshold voltages is applied to a control gate electrode of the transistor. The logic values 0 or 1 are read out depending on whether or not a current flows through the transistor.
The threshold voltage of the transistor can be set by a floating gate electrode, which is electrically insulated and is disposed between the control gate electrode and a channel region of the transistor. To that end, a voltage drop is produced between the control gate electrode and the channel region or a source/drain region of the transistor, which causes electrons to tunnel into or out of the floating gate electrode. A different charge of the floating gate electrode results in different threshold voltages of the transistor.
The name of the floating gate electrode stems from the fact that the electrode is not connected to a potential, i.e. it “floats”. The name of the control gate electrode stems from the fact that the electrode both controls the programming and serves for reading out the information.
In VLSI technology endeavors are made to increase the packing density of circuit configurations in order to reduce process costs and increase circuit speeds.
In order to avoid short-channel effects in the case of a high packing density, U.S. Pat. No. 5,486,714 proposes an electrically programmable memory cell configuration in which source/drain regions of a transistor which acts as memory cell are disposed on upper parts of two mutually opposite sidewalls of a depression. A channel region of the transistor is U-shaped and runs along the two sidewalls and along a bottom of the depression. A large channel length is obtained by this configuration in the case of a high packing density. A floating gate electrode adjoins four sidewalls and the bottom of the depression. The depression is provided with a thermally grown gate oxide in the region of the channel region. In order to reduce the capacitance formed by the floating gate electrode and the channel region, the gate oxide is somewhat thicker on the two sidewalls of the depression than on the bottom of the depression. When information is erased, electrons tunnel only at the bottom of the depression. Disposed above the floating gate electrode is a control gate electrode, which is isolated from the floating gate electrode by a second dielectric. The control gate electrode is part of a word line running perpendicularly to a connecting line between the source/drain regions. The floating gate electrode overlaps the surface of the substrate outside the depression. One of the source/drain regions is connected to a bit line via a contact. The fact that only a very small read current is available, on account of the in some parts thick gate oxide, is disadvantageous.
A further memory cell configuration is described in U.S. Pat. No. 5,392,237. In this case, the floating gate electrode is likewise disposed in a depression and adjoins four sidewalls of the depression. Insulating structures are disposed on the two sidewalls on which the source/drain regions are not disposed. The gate oxide has a uniform thickness. The source region contains a first part and a second part. The first part is disposed underneath the second part and has a lower dopant concentration than the second part. The first part adjoins the channel region. The first part and the second part adjoin a sidewall of the depression.
U.S. Pat. No. 5,567,635 describes an electrically fen programmable memory cell configuration in which a memory cell contains a MOS-FET, a floating gate electrode and a control gate electrode. The floating gate electrode is disposed on four sidewalls and a bottom of a depression. Two source/drain regions of the MOS-FET adjoin two mutually opposite sidewalls of the depression. Insulating structures adjoin the remaining two sidewalls of the depression. A channel region is disposed at the bottom of the depression. The MOS-FET is a planar transistor. The floating gate electrode is electrically insulated from the MOS-FET by a first dielectric. The first dielectric is thinner on the two sidewalls adjoined by the source/drain regions than on the bottom of the depression. Electrons tunnel only at the two sidewalls of the depression. The floating gate electrode acts as gate electrode of the MOSFET. The control gate electrode is part of a word line running parallel to a connecting line between the two source/drain regions. Japanese Patent JP 1-115164 describes an electrically programmable memory cell configuration in which source/drain regions of a transistor adjoin sidewalls of a depression. The sidewalls and a bottom of the depression are provided with a first dielectric. Adjoining the first dielectric is a floating gate electrode on which a second dielectric and a control gate electrode are disposed. During the writing and art reading of information, electrons tunnel at upper and at lower edges of the depression between the floating gate electrode and the source/drain regions of the transistor.
A coupling ratio is the ratio between a capacitance formed by a control gate electrode and a floating gate electrode and a capacitance formed by the floating gate electrode and a channel region and also source/drain regions of a transistor, that is to say by the floating gate electrode and the substrate. The coupling ratio should be as large as possible in order that tunneling can be triggered even at low operating voltages.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide an electrically programmable memory cell configuration and a method for fabricating it which overcome the above-mentioned disadvantages of the prior art devices and methods of this general type, which has a large coupling ratio in comparison with the prior art and can nevertheless be fabricated with a high packing density.
With the foregoing and other objects in view there is provided, in accordance with the invention, an electrically programmable memory cell configuration. The memory cell configuration includes a substrate having a surface and depressions each with a bottom and mutually opposite sidewalls formed therein. A plurality of memory cells having planar it transistors are disposed in the substrate and each of the memory cells has a planar transistor. The planar transistor has two source/drain regions adjoining two of the sidewalls of the depression. A channel region is disposed in the substrate at least part of the bottom of the depression. A first dielectric is disposed on the bottom of the depression in a region of the channel region, the channel region has a cross section that is parallel to the surface of the substrate and intersects the two source/drain regions. A floating gate electrode adjoins the first dielectric and is partially disposed on at least two of the mutually opposite sidewalls of the depression and the depression is constricted but not filled by the floating gate electrode. A second dielectric layer is provided. A control gate electrode is disposed above the floating gate electrode and is insulated from the floating gate electrode by the second dielectric. An insulation layer is disposed on two of the sidewalls of the depression for preventing a capacitance between the two source/drain regions and the floating gate electrode, and parts of the floating gate electrode disposed on the two of the sidewalls of the depression adjoin the insulation layer.
In an electrically programmable memory cell configuration according to the invention, the substrate contains memory cells each having a planar transistor. The channel region of the transistor is disposed in the substrate at at least part of the bottom of the depression that is provided wi
Hofmann Franz
Willer Josef
Booth Richard
Greenberg Laurence A.
Infineon - Technologies AG
Locher Ralph E.
Stemer Werner H.
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