Electrically programmable memory cell array, using charge...

Details Electrically programmable memory cell array, using charge... Electrically programmable memory cell array, using charge...

1997-01-08

2001-02-20

Chaudhuri, Olik (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S331000, C438S259000, C438S270000

Reexamination Certificate

active

06191459

ABSTRACT:

BACKGROUND OF THE INVENTION
Field of the Invention
For many electronic systems, memories are needed into which the data can be written in fixed fashion, once and for all, in digital form. Such memories are known as OTP memories, among other names.
For large amounts of data, such as the digital storage of music or photographs, in particular, plastic disks, so-called compact disks, coated with aluminum are often used as memories. These disks have two kinds of dotlike indentations in the coating, which are assigned to the logical values of 0 and 1. The information is digitally stored in the arrangement of these indentations. The indentations are generated with the aid of a laser, for instance. This means that the compact disks are writeable once and for all.
To write or read a compact disk, the disk is mechanically rotated in a read/write unit. The dotlike indentations are scanned as the information is read via a laser diode and a photo cell. Typical scanning rates are 2×40 kHz. To write the information, the laser diode is operated at higher energy, causing a change in the absorbent layer of the compact disk and thereby forming an indentation. Approximately 5 Gbits of information can be stored on one plastic disk.
The read/write unit includes moving parts that wear mechanically, take up comparatively much volume, permit only slow data access, and consume large amounts of current. Moreover, the read/write unit is vulnerable to jarring and is therefore suitable for mobile systems only to a limited degree.
Electrically programmable semiconductor-based memories, especially of silicon, and known as EEPROMs or flash memories, are often used for storing smaller quantities of data. In electrically programmable memory cell arrays, the storage of the information is usually accomplished by providing, between the gate and the channel region of the MOS transistors, a floating gate that can be acted upon by an electrical charge or a double layer of SiO
2
and Si
3
N
4
as a gate dielectric, at whose boundary layer electric charge carriers can be firmly captured at traps. The threshold voltage of the MOS transistor is dependent on the charge located at the floating gate or the adhesion points. This property is utilized for the electric programming (see for example S. M. Sze, Semiconductor Devices, John Wiley & Sons, pp. 486-490).
In readout of the memory cell array, the individual memory cells are selected via a word line. The gate electrode of each of the MOS transistors is connected to a respective word line. The input of each MOS transistor is connected to a reference line and the output is connected to a bit line. In the reading operation, it is assessed whether a current is flowing through the transistor or not. The logical values of 0 and 1 are assigned accordingly.
Technologically, the storage of 0 and 1 in these memories is accomplished in that the MOS transistors each have different threshold voltages, depending on the information stored in them.
These known silicon memories typically have a planar layout. This requires minimal surface area per memory cell, on the order of about 6 to 8 F
2
, where F is the smallest feasible Structural size for the particular technology employed. Planar read-only silicon memories are thus limited, in 0.4 &mgr;m technology, to memory densities of around 1 bit/&mgr;m
2
.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a electrically programmable memory cell array and process for producing it, which overcomes the above-mentioned disadvantages of the heretofore-known devices and methods of this general type, which provides increased memory density and which can be produced with only a few production steps and a high yield. It is a further object to propose a suitable process for producing such a memory cell array.
With the foregoing and other objects in view there is provided, in accordance with the invention, an electrically programmable memory cell array, comprising:
a semiconductor substrate having a main face, and a cell field with a plurality of memory cells disposed on the main face of the semiconductor substrate;
the memory cells including at least one MOS transistor disposed vertically relative to the main face, the MOS transistor having a gate dielectric formed of a material with charge carrier traps.
In other words, the memory cell array of the invention includes a cell field with memory cells in a semiconductor substrate, preferably of monocrystalline silicon, or in a silicon layer of an SOI substrate. The memory cells include a vertical MOS transistor which has a gate dielectric of a material with charge carrier traps. These traps have the properties of trapping charge carriers and especially electrons. For the electrical programming, the MOS transistors are wired in such a way that charge carriers corresponding to the information to be stored enter the gate dielectric and are trapped by the traps.
The programming of the memory cell array is done after production by injecting electrons. This can be done by either Fowler-Nordheim tunneling or by hot electron injection.
By reversing the polarities in the Fowler-Nordheim tunneling, charge carriers can be removed from the traps, thereby changing the programming of the memory cell array.
To store data in digital form, the MOS transistors are programmed in such a way that they have two different threshold voltages. If the read-only memory cell array is to be used for majority logic, then the gate dielectric is acted upon in programming, by corresponding voltage and time conditions, with different charge quantities in such a way that the MOS transistors, depending on the information entered, have more than two different threshold voltages.
In accordance with an added feature of the invention, the gate dielectric is embodied as a multiple layer, in which at least one layer is provided which, in comparison with at least one further layer in the multiple layer, has an increased charge carrier trapping cross section. The traps are localized at the boundary face between two layers. Preferably, the dielectric multiple layer includes an SiO
2
layer, an Si
3
N
4
layer, and an SiO
2
layer (so-called ONO). Alternatively, the gate dielectric, in its form as a multiple layer, may comprise other materials, where the layer having the increased charge carrier trapping cross section for instance comprises Si
3
N
4
, Ta
2
O
5
, Al
2
O
3
or TiO
2
, and the adjacent layer comprises SiO
2
, Si
3
N
4
or Al
2
O
3
. The multiple layer may also have more than three layers, or fewer than three layers.
In accordance with an additional feature of the invention, the gate dielectric may include a dielectric layer, for instance of SiO
2
, in which foreign atoms, such as W, Pt, Cr, Ni, Pd, Si or Ir are incorporated. The incorporated foreign atoms can be incorporated by implantation, by addition upon an oxidation, or by diffusion. The incorporated foreign atoms in this case form the traps.
In accordance with a further feature of the invention, a plurality of substantially parallel striplike insulation trenches are provided in the cell field. The insulation trenches extend over the entire cell field. The memory cells are each disposed on opposed edges of the insulation trenches. The face of the memory cells overlaps the respective edge.
Striplike doped zones, doped with opposite conductivity to the semiconductor substrate, are disposed on the bottom of the insulation trenches and on the main face of the semiconductor substrate, in each case between adjacent insulation trenches.
The striplike doped zones extend parallel to the insulation trenches over the entire cell field. The vertical MOS transistors of the memory cells are embodied such that one striplike doped zone extending on the bottom of an insulation trench and one striplike doped zone disposed between the insulation trench and the adjacent insulation trench on the main face together each form one of the source/drain zones of the MOS transistor. The gate dielectric and the gate electrode of the MOS transistor are disposed in a hole

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