Electrically programmable, electrically erasable memory array ce

Details Electrically programmable, electrically erasable memory array ce Electrically programmable, electrically erasable memory array ce

1991-08-06

1992-12-01

Hille, Rolf

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

365900, 365185, 257321, 257389, H01L 2968, H01L 2978, H01L 2940, H01L 2934

Patent

active

051683350

ABSTRACT:
A pair of electrically erasable, electrically programmable memory cells are formed at a face of a semiconductor layer (10) and include respective source regions (30a, 30b), a shared drain region (28) and respective channel regions (38a, 38b). Each cell has a floating gate conductor (46a, 46b) that controls the conductance of a respective subchannel region (74a, 74b) and may be programmed through Fowler-Nordheim electron tunneling through a respective tunnel oxide window (40a, 40b) from a respective source region (30a, 30b). A field plate conductor (40a) controls the conductance of respective subchannel regions (70a, 70b) within each channel region (38a, 38b). A word line or control gate conductor (62) is insulatively disposed adjacent respective third, remaining channel subregions (53a, 53b) and further is disposed insulatively adjacent the floating gates (46a, 46b) to program or erase them.

REFERENCES:
patent: 4750024 (1988-06-01), Schreck
patent: 4853895 (1989-08-01), Mitchell et al.
patent: 4907197 (1990-03-01), Uchida
patent: 4912676 (1990-03-01), Paterson et al.
patent: 4924437 (1987-05-01), Paterson et al.
patent: 4947222 (1990-08-01), Gill et al.

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