Electrically programmable and erasable semiconductor memory and

Details Electrically programmable and erasable semiconductor memory and Electrically programmable and erasable semiconductor memory and

1992-11-03

1993-07-13

Wojciechowicz, Edward

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257382, 257390, 257401, H01L 2968

Patent

active

052276520

ABSTRACT:
A semiconductor memory having non-volatile memory cells which can be electrically programmed and erased by means of tunnelling current (EEPROM) with a floating-gate transistor, the cells being arranged in memory cell groups of n lines and m columns each, n cells being connected in series, which serial connection forms the bit line for the columns of a cell block, while the control gate is common to m memory cells of one line of the cell block situated next to one another and forms the word line for the line in the memory cell group. The regions (injector regions) of the n cells of a column of a memory cell group situated below the gate oxide are interconnected and thus form a programming line which is separated from the source and drain zones of the floating-gate transistors. The result is a reduction in the programming voltage to be applied, since the programming voltage applied to each cell of a column is independent of the programming condition of the cells of a column. In addition, this renders it possible to program the cells in a random manner.

REFERENCES:
patent: 4962481 (1990-10-01), Choi et al.
patent: 4996668 (1991-02-01), Peterson et al.
patent: 5008856 (1991-04-01), Iwahashi
"IEEE Journ. of Solid-State Circuits" 24 (1989) 5, 1238-1243.

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