Electrically programmable and erasable semiconductor memory and

Details Electrically programmable and erasable semiconductor memory and Electrically programmable and erasable semiconductor memory and

1991-08-20

1994-01-18

Prenty, Mark V.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

365185, H01L 2968, G11C 1134

Patent

active

052801870

ABSTRACT:
A semiconductor memory includes non-volatile memory cells which can be electrically programmed and erased by means of tunnel current (EEPROM) with a floating-gate transistor, the cell being arranged in memory cell groups of n lines and m columns each, n cells being connected in series, which serial connection forms the bit line for the columns of a cell block. The control gate is common to m memory cells of one line of the cell block situated next to one another and forms the word line for the line in the memory cell group. The floating gate does not extend over the entire width of the channel, so that in each memory cell a parallel transistor is formed which is connected in parallel to the floating-gate transistor and is controlled only by the control gate, which parallel transistor is conducting during reading for each non-selected cell. As a result, the problem of over-erasing is solved even in the case of short access times, without an additional access transistor being required.

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