Electrically programmable and erasable memory device with depres

Details Electrically programmable and erasable memory device with depres Electrically programmable and erasable memory device with depres

1995-04-24

1996-11-19

Limanek, Robert P.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257316, 257317, H01L 29788

Patent

active

055765696

ABSTRACT:
An improved structure and process of fabricating a programmable and erasable read only memory device wherein a thick oxide region is formed on the surface of a semiconductor substrate. The thick oxide region is removed forming a depression in the surface. Impurity ions are implanted into the depression forming a lightly doped source region. A tunnel oxide layer is formed on the substrate surface. Next, the floating gate layer is formed on the tunnel oxide layer which at least partially overlies the lightly doped source region. A gate isolation layer and control gate layer are formed over the floating gate layer. Subsequently, the source and drain regions are formed in the substrate on opposite sides of the gate structure. A dielectric layer is formed over the control gate region and substrate. Contact opening are formed. Electrical contacts and metallurgy lines with appropriate passivation are formed that connect the source, drain and gate elements to form an electrical programmable memory device.

REFERENCES:
patent: 4622737 (1986-11-01), Ravaglia
patent: 5108937 (1992-04-01), Tsai et al.
patent: 5336913 (1994-08-01), Kakiuchi et al.
patent: 5376572 (1994-12-01), Yang et al.
patent: 5502321 (1996-03-01), Matsushita
"Optimization of a Source-Side-Injection FAMOS Cell for Flash EPROM Application", David R. Y. Lui et al, IEDM Tech. DIG. 1991 pp. 315-318.

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