Electrically porous on-chip decoupling/shielding layer

Details Electrically porous on-chip decoupling/shielding layer Electrically porous on-chip decoupling/shielding layer

2002-03-06

2003-02-11

Clark, Jasmine J B (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S774000, C257S750000, C257S763000, C257S764000, C257S758000

Reexamination Certificate

active

06518670

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to semiconductor devices and more particularly to providing protection of conductors on a semiconductor device from interference caused by digital switching noise or other unwanted transient signals.
2. Description of Related Art
A challenge encountered in System-On-Chip (SOC) mixed signal applications is the problem of isolating digital switching noise from small signal analog circuits. It is essential that transient noise signals induced by switching waveforms be kept out of small signal analog circuits, to avoid modulation or pumping of the analog functions by the digital waveform.
In another environment, RF analog single chip applications require that various sections of the chip be isolated from one another.
For example, in most devices RF energy in one circuit needs to be prevented from coupling into adjacent RF circuits, either at the same frequency or at different frequencies, when such coupling of RF energy can lead to undesired mixing products and spurious responses. In single chip designs employing RF power amplifiers, feedback from the output amplifier to lower signal level circuits must be avoided.
In yet another example, in DRAM (Dynamic Random Access Memory) and eDRAM (embedded-DRAM) applications, noise in sense amplifier regions must be minimized. This is especially true with open bitline architectures, since common mode noise rejection provided by the folded bitline architecture is not realized. Advanced DRAM cell layouts of 6F
2
area or less do not provide for folded bitline architecture with a single bitline wiring level. For such DRAM and eDRAM designs, the present invention provides for reduced coupling noise in the sense amplifier circuits.
Well known conventional approaches for decoupling and shielding circuits from each other rely on fabricating discrete decoupling capacitors in the silicon substrate such as gate oxide capacitors or trench capacitors and by employing layouts which increase the distance between a sensitive circuit and sources of noise. Accordingly, decoupling capacitors have been formed within metal wiring levels in the past. However, since the decoupling capacitors have been formed by discrete elements, there is an excessive concentration of the capacitance at specific points in the structure. Moreover, no distributed resistors are included in the structures, and no resistance intentionally incorporated into the capacitive structures.
U.S. Pat. No. 5,285,017 of Gardner describes “Embedded Ground Plane and Shielding Structures Using Sidewall Insulators in High Frequency Circuits Having Vias,” wherein a metallic shielding layer is formed between two adjacent metal wiring levels, but no attempt is made to enhance the interlayer capacitance to improve the decoupling effect.
U.S. Pat. No. 5,472,900 of Vu et al. entitled “Capacitor Fabricated on a Substrate Containing Electronic Circuitry” teaches a structure including a decoupling capacitor formed between two metallic capacitor plates that were deposited within the wiring layers above the semiconductor substrate. The decoupling capacitance is achieved by providing a discrete thin silicon dioxide (SiO
2
) layer formed on horizontal surfaces between the two plates. Since no series resistance is integrated into the structure to improve the decoupling effect at lower frequencies, discrete resistors would need to be formed within the silicon substrate to achieve a modest improvement in the decoupling effect.
Commonly assigned U.S. Pat. No. 5,668,399 of Cronin et al. entitled “Semiconductor Device with Increased On-Chip Decoupling” describes a decoupling capacitor structure formed of a set of horizontal, parallel plates separated by a thin dielectric.
See commonly assigned U.S. Pat. No. 6,140,226 of Grill et al. for “Dual Damascene Processing for Semiconductor Chip Interconnects”.
SUMMARY OF THE INVENTION
An object of this invention is to provide an improved decoupling effect in electronic integrated circuit devices.
Another object of this invention is to provide improved metal wiring between levels on a chip.
Another object of this invention is to form Resistive-Capacitive (RC) decoupling networks in the closest possible proximity to the locations where they are required in electronic-integrated circuit devices.
Glossary
Electrical porosity—a structure is electrically porous when there is an array of electrical conductors which extend through the dielectric structure that permit electric current to flow through many “pores” in the structure. The array of electrical conductors can include an array of resistive studs or the like which pass or extend down through the dielectric structure permitting the electrical current to flow through the electrical-pores as a fluid flows through mechanical pores.
In accordance with this invention, distributed resistance and capacitance are formed between two metal wiring levels on a chip.
Further in accordance with this invention, a distributed RC decoupling network is integrated between two metal wiring levels on a chip.
Accordingly, an electrically porous structure is formed in accordance with this invention providing reduced noise among adjacent circuits, thereby enabling closer placement of circuit functions and higher overall density.
This invention differs from the prior art described above in that it provides a structure and method for fabricating a electrically-porous decoupling/shielding layer between upper and lower on-chip bus wiring layers. The invention achieves enhanced decoupling capacitance by forming an integrated, distributed capacitor-resistor structure on the sidewall surfaces of a conductor lying between the top wiring layers and bottom wiring layers. The structure and process is amenable to integration with dielectric materials having permittivity higher than SiO
2
, e.g. silicon-nitride (Si
3
N
4
), tantalum pentoxide (Ta
2
O
5
), zirconium oxide (Zr
2
O
5
), aluminum oxide (Al
2
O
3
) and barium strontium titanate (BaSrTiO
3
).
In summary, in accordance with this invention the sidewalls of a wiring level include distributed capacitance and resistance integrated into the sidewall structures to form distributed, integrated resistance-capacitance filter devices which preferably provide the improvement of electrical porosity.
Furthermore, since the structure of this invention integrates a resistive element within the structure forming the capacitor, an integrated, distributed RC network circuit is achieved. Such a distributed RC network circuit provides for decoupling and shielding which is more effective than the existing art because the noise and interference signals are filtered within very close proximity to the location which is the source of the disturbances which generate the noise and interference signals.
In accordance with this invention, a semiconductor device with interconnected conductor lines includes a plurality of lower conductor lines formed on a lower level each having a top surface and a plurality of resistive studs with sidewalls, lower ends and upper ends. Each resistive stud is formed over the top surface of a lower conductor line in electrical and mechanical contact therewith at the lower end thereof. A plurality of intermediate conductor lines are formed laterally between the resistive studs, with each intermediate conductor line being separated from each adjacent stud by a capacitor dielectric layer. A plurality of the upper conductor lines formed on a upper level each having a lower surface in contact with the upper end of a corresponding one of the resistive studs. Dielectric material is formed about the intermediate conductor for electrically insulating and separating the intermediate conductor lines from the lower conductor lines and the upper conductor lines.
In accordance another aspect of this invention a semiconductor device included interconnected conductor lines. A lower Interlayer Dielectric (ILD) layer has a top surface formed on the substrate. A plurality of lower conductor lines are formed on the top surface of the lower ILD la

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