Electrically erasable read only memory

Static information storage and retrieval – Read/write circuit – Bad bit

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Details

36518901, 371 211, G11C 1600

Patent

active

055351620

ABSTRACT:
In an electrically erasable programmable ROM in which written data contains in a very limited part high-frequency reload data, the memory capacity is reduced in the following new way. An address detecting circuit (12) detects whether or not designated write addresses are within a predetermined range and discriminates the write object data, which is to be high-frequency reload data, if the designated write addresses are within the predetermined range as the result of detection. Then, three sets of identical data (D.sub.7 to D.sub.0) prepared by a data creating circuit (11) are overwritten respectively in three different memory cells (A.sub.0, A.sub.0 ', A.sub.0 "). In data reading, the individual data are read from the respective memory cells, and one of the data decided by a majority logical circuit (15) is outputted as read data.

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