Electrically erasable PROM (E.sup.2 PROM) with thin film periphe

Details Electrically erasable PROM (E.sup.2 PROM) with thin film periphe Electrically erasable PROM (E.sup.2 PROM) with thin film periphe

1994-05-24

1996-02-20

Limanek, Robert P.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257326, 257372, 257 67, 36518501, H01L 2702

Patent

active

054931398

ABSTRACT:
An Electrically Erasable PROM (E.sup.2 PROM) according to the present invention includes a semiconductor substrate of a first conductivity type having a field oxide formed on a predetermined region of the main surface thereof; a memory section formed on the semiconductor substrate; and a peripheral circuit section formed in the peripheral of the memory section, wherein the peripheral circuit section has a CMOS structure in which an N-channel MOS transistor and a P-channel MOS transistor are connected to each other in a complementary manner; one of the N-channel MOS transistor and the P-channel MOS transistor is a thin film transistor formed on the field oxide and the other is a MOS transistor formed on the semiconductor substrate; and the memory section includes a plurality of non-volatile transistors formed on the semiconductor substrate.

REFERENCES:
patent: 4593453 (1986-06-01), Tam et al.
patent: 5057889 (1991-10-01), Yamada et al.
patent: 5223451 (1993-06-01), Uemura et al.
patent: 5243559 (1993-09-01), Murai
patent: 5294811 (1994-03-01), Aoyama et al.
Koyama, "A Novel Cell Structure for Giga-bit EPROMs and Flash Memories Using Polysilicon Thin Film Transistors", 1992 Symposium on VLSI Technology Digest Technical Papers, pp. 44-45.

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