Electrically erasable programmable read-only memory with thresho

Details Electrically erasable programmable read-only memory with thresho Electrically erasable programmable read-only memory with thresho

1991-03-28

1993-10-12

Pascal, Robert J.

Static information storage and retrieval

Read/write circuit

Including reference or bias voltage generator

365185, G11C 1140

Patent

active

052532062

ABSTRACT:
A NAND cell type electrically erasable programmable read-only memory has NAND cell units. Each NAND cell unit has a series array of floating gate type metaloxide semiconductor field effect transistors as memory cell transistors. The first-stage memory cell transistor is connected at its gate to a corresponding bit line via a first select transistor The last-stage memory cell transistor is connected at its source to a common source line by means of a second select transistor. The common source line is connected with a test circuit to be used for measuring the distribution of threshold values of the memory cell transistors in the erasing state. The test circuit temporarily applies the common source line with a positive bias voltage of a predetermined potential level so that the potential of the control gate of a selected memory cell transistor is set at to 0 volt. As a result, the threshold value of the EEPROM in the erasing state can be measured without using any negative potential.

REFERENCES:
patent: 4799195 (1989-01-01), Iwahashi et al.
patent: 4903236 (1990-02-01), Nakayama et al.
patent: 4939690 (1990-07-01), Momodomi et al.
patent: 4959812 (1990-09-01), Momodomi et al.
patent: 4996669 (1991-02-01), Endoh et al.
Imondi et al, A 5V-Only 256k Bit CMOS Flash EEPROM, ISSCC, Feb. 16, 1989, pp. 132-133.
Momodomi et al, A High Density NAND EEPROM with Block-Page Programming for Microcomputer Applications, IEE 1989 Custom Integrated Circuits Conference, pp. 10.1.1-10.1.4, May 15-18, 1989.

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