Electrically erasable programmable read-only memory with thresho

Details Electrically erasable programmable read-only memory with thresho Electrically erasable programmable read-only memory with thresho

1998-09-02

2000-06-27

Tran, Andrew Q.

Static information storage and retrieval

Floating gate

Particular biasing

36518521, 36518517, 36518518, G11C 1606

Patent

active

060814543

ABSTRACT:
A NAND cell type electrically erasable programmable read-only memory has a memory array section containing NAND cell units. Each NAND cell unit has a series array of floating gate type metal-oxide semiconductor field effect transistors as memory cell transistors. The memory section is associated with a control-gate controller, a data-latch circuit, a sense amplifier section, and a data comparator, which is connected via an output buffer to a verify-termination detector. When a data is once written into a selected memory cell in a data programming mode, a specific biasing voltage is applied to the selected cell so that the actual electrical data write condition of the selected memory cell is verified. If the comparator detects that the verified write condition is dissatisfied, data-rewriting operations are repeatedly executed by additionally supplying the selected cell with a suitable voltage which compensates for the dissatisfaction of the verified write condition in the selected memory cell transistor.

REFERENCES:
patent: 4677590 (1987-06-01), Arakawa
patent: 4939690 (1990-07-01), Momodomi et al.
patent: 4959812 (1990-09-01), Momodomi et al.
patent: 4980861 (1990-12-01), Herdt et al.
patent: 4996669 (1991-02-01), Endoh et al.
patent: 5172338 (1992-12-01), Mehrotra et al.
patent: 5357462 (1994-10-01), Tanaka et al.
patent: 5361227 (1994-11-01), Tanaka et al.
patent: 5825690 (1998-10-01), Saitoh
"Bipolar/Mos Memories Data Book", Advanced Micro Devices, ISSN 0888-4714, pp. 6-1--6-14, 1986.
SEEQ Data Book 1988/89, SEEQ Technology, Inc., pp. 3-1--3-7.
Kynett et al., "An In-System Reprogrammable 32Kx8 CMOS Flash Memory", IEEE Journal of Solid-State Circuits, vol. 23, No. 5, Oct. 1988, 1157-1163.
IBM Technical Disclosure Bulletin, vol. 29, No. 9, Feb. 1987, pp. 4145 and 4146, "EPROM Programming Device".
IEEE, J. Solid-State Circuits, vol. 24, pp. 1259-1263, Oct. 1989. V. Kynett et al., "A 90-ns One-Million Erase/Program Cycle 1-Mbit Flash Memory".
T. Tanaka et al., "A 4-Mbit NAND-WWPROM with Tight Programmed Vt Distribution," in 1990 Symposium on VLSI Circuits Digest of Technical Papers, pp. 105-106, Jun. 1990.

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