Static information storage and retrieval – Read/write circuit – Erase
Patent
1991-09-23
1994-01-18
LaRoche, Eugene R.
Static information storage and retrieval
Read/write circuit
Erase
365185, 36523003, G11C 1602
Patent
active
052804542
ABSTRACT:
An EEPROM includes an array of memory cells divided into a plurality of memory blocks in a semiconductor well region in a substrate. Each block includes series arrays of FATMOS transistors each acting as one memory cell, wherein binary information may be stored in a selected cell transistor by causing carriers to tunnel between the floating gate thereof and the well region. In each block, word lines are connected to the control gates of cell transistors; control lines are to select transistors provided in the series arrays of cell transistors, with which bit lines are associated. A block-erase operation is performed such that a desired one of the memory blocks is selected for erase, while forcing the remaining memory blocks to remain non-erased. To do this, a first voltage is applied to those of the word lines of the selected block, while applying a second voltage to the remaining word lines of the non-selected blocks, the control lines of all the blocks, and the well region.
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T. Tamaka et al, "A 4-Mbit NAND-EEPROM with Tight Programmed Vt Distribution", 1990 Symposium on VLSI Circuits Digest of Technical Papers, pp. 105-106, Jun. 1990.
Iwata Yoshihisa
Momodomi Masaki
Sakui Koji
Tanaka Tomoharu
Dinh Son
Kabushiki Kaisha Toshiba
LaRoche Eugene R.
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