Electrically erasable programmable read-only memory with an arra

Details Electrically erasable programmable read-only memory with an arra Electrically erasable programmable read-only memory with an arra

1991-10-23

1994-10-11

Nguyen, Viet Q.

Static information storage and retrieval

Systems using particular element

Semiconductive

365185, 365218, 257314, 257321, 257322, G11C 700, G11C 1140, H01L 2710

Patent

active

053553322

ABSTRACT:
A floating gate tunneling metal oxide semiconductor transistor is formed on a semiconductive substrate as a cell of electrically erasable programmable read-only memory. The transistor includes a source and a drain spaced apart to define a channel region therebetween in the substrate. An insulated floating gate at least partially overlies the channel region and is capacitively coupled with the substrate. A control gate is insulatively disposed above the conductive layer and spans the channel region. The withstanding voltage of the drain is specifically set to range from a first voltage adapted to be applied to the drain during a read operation to a second voltage applied thereto for forcing the conductive layer to discharge.

REFERENCES:
patent: 4996571 (1991-02-01), Kume et al.
patent: 5075890 (1991-12-01), Itoh et al.
patent: 5095461 (1992-03-01), Miyakawa et al.
Y. Iwata, et al., "A High-Density Nand EEPROM With Block-Page Programming for Microcomputer Applications", IEEE Journal of Solid-State Circuits, vol. 25, No. 2, Apr. 1990, pp. 417-423.
H. Kume, et al., "A Flash-Erase EEPROM Cell With an Asymmetric Source and Drain Structure", IEEE Tech. Dig. of IEDM, 1987, pp. 560-563.
K. Yoshikawa, et al., "A Reliable Profiled Lightly Doped Drain (PLD) Cell for High-Density Submicrometer EPROM'S and Flash EEPROM'S", IEEE Transactions on Electron Devices, vol. 37, No. 4, Apr. 1990, pp. 999-1005.
Wu-Shiung FENG et al., "MOSFET Drain Breakdown Voltage", IEEE Electron Device Letters, vol. EDL-7, No. 7, Jul. 1986, pp. 449-450.

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