Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – With pn junction isolation
Reexamination Certificate
2007-11-27
2007-11-27
Soward, Ida M. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
With pn junction isolation
C257S297000, C257S327000, C257S336000, C257S344000, C257S349000, C257S405000, C257S406000, C257S408000, C257S410000, C257S411000, C257S639000, C257S649000, C257S760000, C257S900000
Reexamination Certificate
active
11146777
ABSTRACT:
An asymmetrically doped memory cell has first and second N+ doped junctions on a P substrate. A composite charge trapping layer is disposed over the P substrate and between the first and the second N+ doped junctions. A N− doped region is positioned adjacent to the first N+ doped junction and under the composite charge trapping layer. A P− doped region is positioned adjacent to the second N+ doped junction and under the composite charge trapping layer. The asymmetrically doped memory cell will store charges at the end of the composite charge trapping layer that is above the P− doped region. The asymmetrically doped memory cell can function as an electrically erasable programmable read only memory cell, and is capable of multiple level cell operations. A method for making an asymmetrically doped memory cell is also described.
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Hsu Tzu-Hsuan
Lee Ming-Hsiu
Shih Yen-Hao
Macronix International Co. Ltd.
Martine & Penilla & Gencarella LLP
Soward Ida M.
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