Electrically-erasable/programmable nonvolatile semiconductor mem

Details Electrically-erasable/programmable nonvolatile semiconductor mem Electrically-erasable/programmable nonvolatile semiconductor mem

1987-09-09

1988-12-27

Fears, Terrell W.

Static information storage and retrieval

Systems using particular element

Semiconductive

357 236, 365185, G11C 1140

Patent

active

047945621

ABSTRACT:
In an electrically-erasable/programmable nonvolatile semiconductor memory device according to the invention, a one-bit memory cell is constituted by a series circuit of a selecting MOS transistor and a data storage MOS transistor. A floating gate electrode and a control gate electrode are formed in the data storage MOS transistor, One portion of the floating gate electrode is formed on a channel region of the data storage MOS transistor through a gate insulating film. The other portion of the floating gate electrode is formed on a drain region of the data storage MOS transistor through a gate insulating film, a portion of which is sufficiently thinner than the gate insulating film. One and the other portions of the floating gate electrode are structurally separated from each other but are electrically connected with each other on a field region. A control gate electrode having substantially the same shape as that of the floating gate electrode is formed thereon through a gate insulating film.

REFERENCES:
patent: 4278989 (1981-07-01), Baba et al.
patent: 4709255 (1987-11-01), Hartgring et al.
Lucero et al., "A 16 kbit Smart 5 V-Only EEPROM with Redundancy," IEEE Journal of Solid-State Circuits, vol. SC-18, No. 5, pp. 539-544, Oct. 1983.
Japanese Patent Disclosure (Kokai) No. 59-103366, H. Arakawa, Jun. 14, 1984.
Japanese Patent Disclosure (Kokai) No. 59-205763, N. Sumihiro, Nov. 21, 1984.

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