Electrically erasable programmable memory device with improved e

Details Electrically erasable programmable memory device with improved e Electrically erasable programmable memory device with improved e

1994-12-12

1996-05-07

Limanek, Robert P.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257316, H01L 29788

Patent

active

055148905

ABSTRACT:
An improved structure and process of fabricating an electrically erasable programmable read only memory device (EEPROM's) wherein a thick oxide region is formed on the surface of a semiconductor substrate. The thick oxide is removed forming a depression in the surface. Impurity ions are implanted in the depression forming a highly doped tunneling region. A tunnel oxide layer is formed on the substrate surface fully covering the tunneling region. Next, the floating gate layer is formed on the tunnel oxide layer. The gate isolation layer and control gate layer are formed over the floating gate layer. Subsequently, the spaced source and drain regions are formed in the substrate on opposite sides of the gate structure. A dielectric layer is formed over the control gate region and substrate. Contact openings are formed. Electrical contacts and metallurgy lines with appropriate passivation are formed that connect the source, drain and gate elements to form an electrically erasable programmable read only memory device.

REFERENCES:
patent: 4622737 (1986-11-01), Ravaglia
patent: 5108937 (1992-04-01), Tsai et al.
patent: 5210597 (1993-05-01), Kakiuchi et al.
"A Self-Convergence Erasing Scheme for a Simple Stacked Gate Flash EEPROM", IEDM 91, pp. 307-310.

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