Electrically erasable progammable read-only memory with nand cel

Details Electrically erasable progammable read-only memory with nand cel Electrically erasable progammable read-only memory with nand cel

1991-10-09

1993-09-21

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Including reference or bias voltage generator

36518911, 365185, 365104, G11C 1140

Patent

active

052474801

ABSTRACT:
An electrically erasable programmable read-only memory has memory cell blocks, each of which has NAND type cell units associated with the bit lines respectively. Each cell unit has a series-circuit of floating gate type memory cell transistors and a selection transistor provided between the corresponding bit line and the series-circuit of memory cell transistors. A row decoder is provided in common to the memory cell blocks, for generating an "H" level voltage which is supplied to a selection gate control line connected to the selection transistor and to a selected word line or lines in a cell unit. A voltage boost circuit is provided for every memory cell block, for causing the "H" level voltage to increase up to a preselected potential level which is high enough to render the cell transistors conductive. The voltage boost circuit includes a first booster section for the selection gate control line, and a second section for the word lines. The second section operates in response to the output voltage of the first section.

REFERENCES:
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patent: 4980861 (1990-12-01), Herdt et al.
patent: 5075890 (1991-12-01), Itoh et al.
IEEE International Solid-State Circuits Conference, 16, Feb. 1989, Digest of Technical Paper, S. 134, 135.

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