Electrically erasable nonvolatile semiconductor memory that perm

Details Electrically erasable nonvolatile semiconductor memory that perm Electrically erasable nonvolatile semiconductor memory that perm

1994-01-14

1995-03-21

Fears, Terrell W.

Static information storage and retrieval

Systems using particular element

Capacitors

365226, 365900, G11C 1124

Patent

active

054002761

ABSTRACT:
The purpose of the present invention is to provide an electrically erasable nonvolatile semiconductor memory that permits correct data readout despite the occurrence of over-erased memory cells. In the nonvolatile semiconductor memory of the invention, a select transistor whose gate is connected to a word line is provided for each group consisting of a plurality of memory cells, and the sources of the memory cells in the same group are connected to a common source via the select transistor. For writing and erasure, the source-drain relationship is reversed from that previously practiced, so that for writing the drain is grounded and a positive voltage is applied to the source while for erasure the source is grounded and a high voltage is applied to the drain. In a nonvolatile semiconductor memory according to another mode of the invention, a source line is provided independently for every one or a plurality of word lines. For reading, the source line, word line, and bit line to which the memory cell selected for reading is connected are supplied with a lower supply voltage, a higher supply voltage, and a positive voltage lower than the higher supply voltage, respectively, while the source lines and word lines to which the selected memory cell is not connected are supplied with the higher supply voltage and the lower supply voltage, respectively, and the bit lines to which the selected memory cell is not connected are opened.

REFERENCES:
patent: 5136533 (1992-08-01), Harari

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