Electrically erasable dual-injector floating gate programmable m

Details Electrically erasable dual-injector floating gate programmable m Electrically erasable dual-injector floating gate programmable m

1982-04-13

1985-03-05

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Erase

365189, G11C 1300

Patent

active

045035245

ABSTRACT:
An improved electrically erasable semiconductor memory device of the N-channel, MOS, double level poly, programmable, read only memory or EPROM type is provided. The device is an array of cells electrically erased and programmed by dual injection into floating gates which are interposed between the channels and control gates. The electrical erasure or programming of the cells is accomplished by applying selected voltages to the source, drain, control gate and substrate to produce injection of electrons or holes.

REFERENCES:
patent: 3875567 (1975-04-01), Yamazaki et al.
patent: 4308596 (1981-12-01), Takai et al.
patent: 4384349 (1983-05-01), McElroy

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