Electrically erasable charge trap nonvolatile memory cells...

Details Electrically erasable charge trap nonvolatile memory cells... Electrically erasable charge trap nonvolatile memory cells...

2005-09-20

2005-09-20

Ho, Hoai (Department: 2827)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185280, C365S185240, C365S185210, C365S185180

Reexamination Certificate

active

06947330

ABSTRACT:
An electrically erasable charge trap nonvolatile memory cell has an initial threshold voltage, a program voltage that is higher than the initial threshold voltage, and an erase threshold voltage that is lower than the program threshold voltage but is higher than the initial threshold voltage. The programmed electrically erasable charge trap nonvolatile memory cells may be erased by applying an erase voltage for a time interval that is sufficient to lower the threshold voltage the transistor from a program threshold voltage to an erase threshold voltage that is lower than the program threshold voltage, but is higher than the initial threshold voltage. The time interval may be determined by repeatedly performing an endurance test using a time interval that is increased or decreased from an initial time interval, to obtain the time interval that meets an endurance specification, or allows a read to be performed successfully.

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