Electrically erasable and programmable read only memory with an

Details Electrically erasable and programmable read only memory with an Electrically erasable and programmable read only memory with an

1993-03-30

1995-09-05

Trammell, James P.

Excavating

371 401, 395430, H03M 1300

Patent

active

054485789

ABSTRACT:
An electrically erasable programmable read only memory (EEPROM), having error checking and correction circuitry uses a separation circuit to electrically isolate a temporary page buffer memory from a memory array so that better reliability of parity generation and error correction is provided. The EEPROM memory array includes a plurality of bit lines, a plurality of memory cells respectively connected to the bit lines and parity cells. The error check and correction circuit includes a column gate logic, connected to the plurality of bit lines, for temporarily loading randomly input data onto a memory page buffer. The EEPROM processes the data in the page buffer to logically store it as multi-byte data, simultaneously together with appropriate parity bit data corresponding to each multi-byte data set, in the memory array. Because data randomly input to and from the page buffer is selectively, electrically isolated from the memory array, bit errors that would otherwise be caused by defective memory cells, or bit lines, within the memory array, are compensated for in advance.

REFERENCES:
patent: 3668632 (1972-06-01), Oldham, III
patent: 4410988 (1983-10-01), Suelflow et al.
patent: 4672613 (1987-06-01), Foxworthy et al.
patent: 4996690 (1991-02-01), George et al.
patent: 5274647 (1993-12-01), Tanaka

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