Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-12-30
2001-09-18
Bowers, Charles (Department: 2813)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C438S257000, C438S264000
Reexamination Certificate
active
06291854
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device. More particularly, the present invention relates to the fabrication of an electrically erasable and programmable read only memory device and a flash electrically erasable and programmable read only memory (EEPROM) device and the fabrication method therefor.
2. Description of the Related Art
A major component of an EEPROM device is the floating gate in which the potential at the floating gate controls the conductivity along a field effect transistor channel between the source and the drain regions. The floating gate is separated from the substrate by a gate oxide layer, for example, a silicon oxide. A control gate is generally positioned over the floating gate and is capacitively coupled with the floating gate through a dielectric layer. The control gate acts as a word line to enable the reading and writing of a single selected cell.
In general, two basic modes of operation are used for the programming and erasure of an EEPROM device. For the first mode of operation (prior art I), a selected memory cell is programmed (or erased) by holding the control gate, the source and the drain at appropriate voltages. This voltage condition causes hot electrons to be generated. Once these electrons gain sufficient energy and overcome the potential barrier of the gate oxide layer on the channel region (a portion of the substrate lying between the source and drain), they travel from the substrate and are injected into the floating gate by a mechanism referred to as “Channel Hot Electron Injection”. If enough electrons are injected into the floating gate, the threshold voltage of the memory cell is increased and a logic state of “1” or “0” can be stored in the memory cell in the case of a programming operation. Correspondingly, during the erasure (or programming) operation, the control gate, the source and the drain are held at a potential that causes the electrons to tunnel back through the gate oxide layer by the so-called the Fowler-Nordheim tunneling phenomenon to the substrate, usually the source region, reversing the channel hot electron injection of the electrons into the floating gate of the above programming (or erasure) operation.
Another mode of operation (prior art II) for the EEPROM device uses Fowler-Nordheim tunneling to inject electrons into the floating gate and back into the substrate for both the programming and the erasure operations.
Reference is made to
FIG. 1
, which is a schematic, cross-sectional view showing an electrically erasable programmable read only memory device according to the prior art. As shown in
FIG. 1
, programming
114
of selective memory cells of an EEPROM device involves an application of a negative voltage on the control gate
108
and a positive voltage on the drain region
104
, causing the electrons to be injected from the floating gate
106
through gate oxide (not shown in Figure) into the drain region
104
.
Still referring to
FIG. 1
, during the erasure operation
112
, a positive high voltage is applied on the control gate
108
while grounding the source
102
and substrate
100
to cause the electrons to be injected from the source to the floating gate. Table 1 summarizes the operation conditions for an EEPROM according to prior art I and prior art II. As shown in Table 1, a very high voltage (>20 volts) is required for the electrons to pass through the gate oxide layer for the EEPROM device following mode
1
of the erasing operation mentioned in the above (prior art I). Additionally, the erasure speed is low (about 100mS).
TABLE 1
The operation conditions an EEPROM device according to prior art I
and prior art II.
Control
Drain
Source
Operation
Gate
Region
Region
Substrate
prior art I
Erasure
20 V
Floating
Grounded
Grounded
prior art II
Erasure
10-12 V
Floating
−5 V
−5 V
There are several drawbacks associated with using a high voltage in an erasure operation as in prior art I. One such drawback lies in the needs for complicated circuits and manufacturing procedure for a high voltage operation (greater than or equal to 20 V). Furthermore, the high voltage charge pumping circuit required for this type of high voltage operation occupies a substantial area of the substrate.
Furthermore, in a high voltage metal-oxide-silicon-field-effect-transistor (MOSFET), a thick gate oxide layer and a long channel region are required to switch on and off the high voltage. If the thickness of the gate oxide layer is doubled, the manufacturing process becomes complicated. In addition, adjusting the dimension of a MOSFET is not simple. Yet another disadvantage associated with using a high voltage in an erasure operation is that the high voltage violates the low power dissipation requirement for the portable device.
Still referring to
FIG. 1
, alternatively, in the second mode of the flash EEPROM erasure operation (prior art II in Table 1), a negative voltage (approximately −5V) is applied to the source region
102
to reduce the voltage (can be reduced to about 10 V to 12V) that needs to be applied on the control gate
108
. Applying a negative voltage to an N-type source region
102
, however, would require formation of a deeper N-well region (not shown in Figure) underneath the shallow P-well region (not shown in
FIG. 1
, but located under the source region
102
) in the substrate
100
to isolate the biased P-well region. The type of the design, nevertheless, occupies a significant area of the silicon substrate and also complicates the circuitry.
Generally speaking, the two modes of the operation require the high voltage pumping circuit, which occupies a substantial amount of wafer area. They also require many complicated periphery circuits to generate and control the negative voltage.
Furthermore, the EEPROM can be erased in a “flash” or in a bulk mode in which a large block of the memory cells or the entire array of memory cells can be erased simultaneously. This type of EEPROM is known as flash EEPROM. The block size is determined by how many source regions of the memory cells are connected together. In order to preserve the space on the silicon substrate of a flash memory cell, several hundreds to several thousands of the source regions are directly connected to the N+ junction to form a source line without the assistance of a contact window or metal for interconnection. However, when the device dimension is further scaled-down, the junction resistance increases dramatically because of a shallower junction. The high source side resistance further makes the cells, which are far from the source contact, have a positive voltage bias compared to the cells which are near the source contact and are well grounded. The positive voltage on the source side increases the threshold voltage of the memory cell. As a result, the capability to differentiate the information stored as “1” or “0” deteriorates.
SUMMARY OF THE INVENTION
Based on the foregoing, the present invention provides an electrically erasable programmable read only memory device and the method for making such a device in which a plurality of source regions is formed in the substrate. A first dielectric layer is then formed on the substrate covering the source region. After this, a floating gate is formed on the first dielectric layer. A plurality of drain regions is further formed in the substrate, followed by forming a second dielectric layer on the substrate. A control gate is subsequently formed on the second dielectric layer.
In addition, according to this version of the present invention, a sharp-cornered doped polysilicon pillar in conjunction with each source region is formed before covering the source region with the first dielectric layer or is formed during the formation of the source region.
According to the preferred embodiment of the present invention, the doped polysilicon pillar is preferably formed by sequentially forming a first oxide layer and a silicon nitride layer on the substrate. The silicon nitride layer and the first oxide layer are
Bowers Charles
Huang Jiawei
J.C. Patents
Pert Evan
United Microelectronics Corp.
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