Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2000-02-03
2001-02-13
Dinh, Son T. (Department: 2824)
Static information storage and retrieval
Floating gate
Particular biasing
C365S189070
Reexamination Certificate
active
06188610
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 11-027210, filed Feb. 4, 1999, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
This invention relates to a nonvolatile semiconductor memory device such as an electrically erasable and programmable ROM (EEPROM).
A conventional nonvolatile semiconductor memory device, in this example, EEPROM is explained below.
FIG. 1
is a block diagram showing the construction of the conventional EEPROM. In the EEPROM shown in
FIG. 1
, the operation for reading out data stored in memory cells of a cell array
102
is effected as follows.
Address data supplied via an address input bus is input to an address generating circuit
106
via an address input circuit
104
.
The address generating circuit
106
generates a row address based on the input address data and outputs the row address to a row decoder
108
. Further, the address generating circuit
106
generates a column address based on the input address data and outputs the column address to a column decoder
110
. The row decoder
108
and column decoder
110
selects a memory cell to be subjected to the readout operation based on the input row address and column address.
Data of the memory cell selected by the row address and column address is read out by a readout circuit (sense amplifier)
112
via an internal data bus
112
A and input to a data input/output circuit
114
. Then, data input to the data input/output circuit
114
is output to the exterior via a data input/output bus
114
A.
The program operation is effected as follows.
Write input data input to the data input/output circuit
114
via the data input/output bus
114
A is input to a write circuit
116
and data comparator
118
. Verify data read out in the program verify state and the input data are compared with each other in the data comparator
118
before the write operation and the result of comparison is output to an automatic write/erase operation control sequencer (which is hereinafter referred to as an operation control sequencer)
120
.
If the result of comparison by the data comparator
118
indicates that “input data”=“verify data”, the operation control sequencer
120
does not effect the write operation. On the other hand, if “input data”≠“verify data”, the operation control sequencer
120
outputs an operation mode signal, in this example, a signal for specifying the program mode to an internal voltage control circuit
122
, switches a word line potential VWL and column potential VCO from the program verify potential state to the program potential state and then effects the write operation.
After the elapse of a preset program time, the operation control sequencer
120
outputs an operation mode signal, in this example, a signal for specifying the program verify to the internal voltage control circuit
122
, restores the word line potential VWL and column potential VCO to the program verify potential state and then effects the readout operation (program verify) with respect to a memory cell into which data has been written.
Next, input data input to the data input circuit
114
and data read out in the program verify are compared with each other in the data comparator
118
and if every compared bits coincide with each other, the program operation is terminated. On the other hand, if any compared bits which do not coincide with each other are present, the operation control sequencer
120
specifies the write circuit
116
to effect the additional write operation again and thus effects the write operation.
Next, the current-voltage characteristic of the memory cell when the program operation (write operation) is effected is explained.
FIG. 2
is a diagram showing the current-voltage characteristic of the memory cell when data is written into the EEPROM and the current-voltage characteristic of a memory cell which is left as it is after the write operation.
FIGS. 3A
,
3
B are schematic cross sectional views each showing the structure of the memory cell and the electrical state thereof.
Before data is written into the memory cell of the EPROM (in this case, it is assumed that data is erased), the threshold voltage Vth of the memory cell lies in a low level range. After this, if data is written into the memory cell, the threshold voltage Vth is shifted towards the high voltage side and is set to a high voltage as indicated by “A” in FIG.
2
.
After execution of the write operation, it is determined (verified) whether data is correctly written or not by reading out data from the memory cell by use of a voltage higher than the voltage at the read time with a margin contained therein. In the memory cell into which data is written, stress is applied to the memory cell by access for reading or the like and electrons stored in the floating gate are extracted or leaked out.
The state of extraction of electrons stored in the floating gate is explained with reference to
FIGS. 3A
,
3
B. A source (diffusion layer)
132
and drain (diffusion layer)
134
are formed in a semiconductor substrate
130
and a floating gate
136
is formed above the channel region with a gate insulating film
135
disposed therebetween. A control gate
138
is formed above the floating gate
136
with an insulating film
137
disposed therebetween. Immediately after the write operation, electrons are stored in the floating gate
136
as shown in FIG.
3
A. After this, if stress is applied to the memory cell by access for reading or the like, electrons which have been stored in the floating gate
136
are gradually leaked or extracted via the drain
134
as shown in FIG.
3
B. As a result, for example, the current-voltage characteristic as indicated by “B” in
FIG. 2
may be obtained.
If the data readout operation is effected in the state indicated by “B” of
FIG. 2
, data which is the same as that in the programmed state can be read out since the threshold voltage Vth of the memory cell is higher than the voltage at the read time. However, if the data readout operation is effected by use of the voltage which is used for effecting the program verify, there occurs a possibility that the threshold voltage of the memory cell which is originally set as an “L” level cell is set into an “H” level cell and the memory cell is regarded as an erase cell since a cell current which is larger than the reference current can be derived. As a result, erroneous data may be read out.
That is, in a case wherein given data is programmed into a memory cell of the EEPROM in a nonvolatile semiconductor memory device such as the EEPROM and then programmed data is read out, there occurs a possibility that electrons stored in the floating gate may be extracted by stress at the read time or the like while the read operation is repeatedly effected, data will be erroneously recognized, and the reliability of data will be influenced.
In the conventional case, the above problem can be coped with by improving the film quality of an oxide film (tunnel oxide film) constructing the gate insulating film to suppress the amount of electrons which will be extracted or leaked. However, the absolute amount of electrons stored in the floating gate will be reduced as the device will be further miniaturized in the future. Therefore, it will be difficult to cope with the above problem only by improving the film quality of the oxide film.
BRIEF SUMMARY OF THE INVENTION
This invention has been made in order to solve the above problem and an object of this invention is to provide a nonvolatile semiconductor memory device and a data holding method capable of preventing written (programmed) data from being erroneously recognized and enhancing the reliability thereof.
In order to attain the above object, a nonvolatile semiconductor memory device according to this invention comprises nonvolatile memory cells capable of storing data; a readout circuit for reading out data of the memory cell by use of one of a first word line potential and
Kakizoe Kazuhiko
Okawa Toru
Dinh Son T.
Kabushiki Kaisha Toshiba
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
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