Static information storage and retrieval – Read/write circuit – Testing
Patent
1995-08-22
1997-02-11
Canney, Vincent P.
Static information storage and retrieval
Read/write circuit
Testing
371 51, G01R 3128
Patent
active
056027893
ABSTRACT:
An EEPROM for storing multi-level data includes a memory cell array in which electrically erasable and programmable memory cells are arranged in matrix and each of the memory cells has at least three storage states, a write circuit for writing data to the memory cells, first and second write verify means each constituted of a sense amplifier, a data latch circuit and a detection circuit, for verifying an insufficient-written state of a memory cell and an excess-written state of a memory cell, respectively, an additional write circuit for additionally writing data to the memory cell in the insufficient-written state, and an additional erase circuit for additionally erasing data from the memory cell in the excess-written state.
REFERENCES:
patent: 5321699 (1994-06-01), Endoh et al.
Aritome Seiichi
Endoh Tetsuo
Kirisawa Ryouhei
Ohuchi Kazunori
Shirota Riichiro
Canney Vincent P.
Kabushiki Kaisha Toshiba
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