Static information storage and retrieval – Read/write circuit – Erase
Patent
1979-09-06
1981-01-27
Fears, Terrell W.
Static information storage and retrieval
Read/write circuit
Erase
365182, 365185, 307238, G11C 1140
Patent
active
042479185
ABSTRACT:
An electrically erasable nonvolatile memory system comprises nonvolatile memory cells each including one transistor. A plurality of row lines are connected commonly to the control gates of the memory cells arranged in a row direction, respectively. For applying a positive voltage to a selected row line upon data-write or data-read and a negative voltage to a selected row line upon data-erase, a plurality of control circuits are provided. Each control circuit is coupled with a corresponding one of the row lines, with one of outputs of a row decoder selecting a row line and with a control terminal which is commonly coupled to the control circuits. Each control circuit is so constructed as to supply to a corresponding row line with a voltage having a prescribed level corresponding to a voltage level applied to the control terminal.
REFERENCES:
patent: 4172291 (1979-10-01), Owens
Ariizumi Shoji
Iwahashi Hiroshi
Fears Terrell W.
Tokyo Shibaura Denki Kabushiki Kaisha
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