Electrically alterable non-volatile memory with N-bits per cell

Details Electrically alterable non-volatile memory with N-bits per cell Electrically alterable non-volatile memory with N-bits per cell

1995-02-27

1998-06-09

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

36518907, 365168, 365201, G11C 1300

Patent

active

057645710

ABSTRACT:
An electrically alterable, non-volatile multi-bit memory cell has K.sup.n predetermined memory states (K.sup.n >2), where K is a base of a predetermined number system and n is a number of bits stored per cell. Programming of the cell is verified by selecting a reference signal corresponding to the information to be stored and comparing a signal of the cell with the selected reference signal.

REFERENCES:
patent: 3660819 (1972-05-01), Frohman-Bentchkowsky
patent: 3801965 (1974-04-01), Keller et al.
patent: 4004159 (1977-01-01), Rai et al.
patent: 4054864 (1977-10-01), Audaire et al.
patent: 4090258 (1978-05-01), Cricchi
patent: 4122541 (1978-10-01), Uchida
patent: 4139910 (1979-02-01), Anantha et al.
patent: 4149270 (1979-04-01), Cricchi et al.
patent: 4181980 (1980-01-01), McCoy
patent: 4192014 (1980-03-01), Craycraft
patent: 4272830 (1981-06-01), Moench
patent: 4287570 (1981-09-01), Stark
patent: 4300210 (1981-11-01), Chakravarti et al.
patent: 4306300 (1981-12-01), Terman et al.
patent: 4327424 (1982-04-01), Wu
patent: 4357685 (1982-11-01), Daniele et al.
patent: 4388702 (1983-06-01), Sheppard
patent: 4415992 (1983-11-01), Adlhoch
patent: 4449203 (1984-05-01), Adlhoch
patent: 4462088 (1984-07-01), Giuliani et al.
patent: 4495602 (1985-01-01), Sheppard
patent: 4503518 (1985-03-01), Iwahashi
patent: 4558241 (1985-12-01), Suzuki et al.
patent: 4578777 (1986-03-01), Fang et al.
patent: 4586163 (1986-04-01), Koike
patent: 4627027 (1986-12-01), Rai et al.
patent: 4653023 (1987-03-01), Suzuki et al.
patent: 4661929 (1987-04-01), Aoki et al.
patent: 4709350 (1987-11-01), Nakagome et al.
patent: 4733394 (1988-03-01), Giebel
patent: 4771404 (1988-09-01), Mano et al.
patent: 4799195 (1989-01-01), Iwahashi
patent: 4809224 (1989-02-01), Suzuki et al.
patent: 4847808 (1989-07-01), Kobatake
patent: 4853892 (1989-08-01), Hori
patent: 4890259 (1989-12-01), Simko
patent: 4914631 (1990-04-01), Johnson et al.
patent: 4964079 (1990-10-01), Devin
patent: 4989179 (1991-01-01), Simko
patent: 5021999 (1991-06-01), Kohda et al.
patent: 5043940 (1991-08-01), Harari
patent: 5095344 (1992-03-01), Harari
patent: 5163021 (1992-11-01), Mehrotra et al.
patent: 5172338 (1992-12-01), Mehrotra et al.
patent: 5218569 (1993-06-01), Banks
patent: 5258958 (1993-11-01), Iwahashi et al.
patent: 5262984 (1993-11-01), Noguchi et al.
patent: 5268870 (1993-12-01), Harari
patent: 5293560 (1994-03-01), Harari
patent: 5295255 (1994-03-01), Malecek et al.
patent: 5321655 (1994-06-01), Iwahashi et al.
patent: 5351210 (1994-09-01), Saito
patent: 5422845 (1995-06-01), Ong
patent: 5432735 (1995-07-01), Parks et al.
patent: 5434825 (1995-07-01), Harari
patent: 5440505 (1995-08-01), Fazio et al.
patent: 5444656 (1995-08-01), Bauer et al.
patent: 5450363 (1995-09-01), Christopherson et al.
patent: 5457650 (1995-10-01), Sugiura et al.
patent: 5469384 (1995-11-01), Lacey
patent: 5475693 (1995-12-01), Christopherson et al.
patent: 5485422 (1996-01-01), Bauer et al.
patent: 5497119 (1996-03-01), Tedrow et al.
patent: 5506813 (1996-04-01), Mochizuki et al.
patent: 5508958 (1996-04-01), Fazio et al.
patent: 5515317 (1996-05-01), Wells et al.
patent: 5523972 (1996-06-01), Rashid et al.
patent: 5539690 (1996-07-01), Talreja et al.
patent: 5541886 (1996-07-01), Hasbun
patent: 5544118 (1996-08-01), Harari
patent: 5550772 (1996-08-01), Gill
patent: 5568439 (1996-10-01), Harari
patent: 5583812 (1996-12-01), Harari
patent: 5594691 (1997-01-01), Bashir
patent: 5596527 (1997-01-01), Tomioka et al.
M. Bauer et al., A Multilevel-Cell 32Mb Flash Memory, 1995 IEEE International Solid-State Circuits Conference, Session 7, Paper TA7.7.
John A. Bayliss et al., The Interface Processor for the 32b Computer, 1981 IEEE International Solid-State Circuits Conference, Feb. 1981, at 116-117.
Christoph Bleiker & Hans Melchior, A Four-State EEPROM Using Floating-Gate Memory Cells, IEEE Journal of Solid-State Circuits, vol. SC-22, No. 3, Jun. 1987, at 260-263.
Raymond A. Heald & David A. Hodges, Multilevel Random-Access Memory Using One Transistor Per Cell, IEEE Journal of Solid-State Circuits, vol. SC-11, No. 4, Aug. 1976, at 519-528.
David A. Rich, A Survey of Multivalued Memories, IEEE Transactions on Computers, vol. C-35, No. 2, Feb. 1986, at 99-106.
R.S. Withers et al., Nonvolatile Analog Memory in MNOS Capacitors, IEEE Electron Device Letters, vol. EDL-1, No. 3, Mar. 1980, at 42-45.

Affiliated with

Also associated with

Rating

Electrically alterable non-volatile memory with N-bits per cell does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Electrically alterable non-volatile memory with N-bits per cell, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Electrically alterable non-volatile memory with N-bits per cell will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2209375