Electrically alterable interconnection

Details Electrically alterable interconnection Electrically alterable interconnection

1976-05-07

1978-05-30

Hecker, Stuart N.

Static information storage and retrieval

Read/write circuit

Bad bit

307247R, 365184, 365154, G11C 506, G11C 2900

Patent

active

040927334

ABSTRACT:
An electrically alterable, non-volatile interconnect selectively connects and disconnects microcircuit elements formed on a wafer. The interconnect is formed on the same wafer as the microcircuit elements during the circuit fabrication process to permit electrically controlled reconfiguration of the microcircuit elements on the wafer. This enables wafer scale integration by permitting defective circuit elements to be bypassed and operable, redundant circuits to be substituted for them. MNOS memory transistors provide non-volatile storage of the chosen conductivity state of each interconnect, in the form of impedance differences. In a preferred embodiment, the impedance differences set a flip-flop whose output enables a gate. The gate may include amplification of the signals gated. In one phase of the cycle of operation, the chosen conductivity state of the interconnect may be read into the MNOS memory through the flip-flop.

REFERENCES:
patent: 3755791 (1973-08-01), Arzubi
patent: 3913072 (1975-10-01), Catt
Chin et al., Reversible On-Chip Redundancy Scheme, IBM Technical Disclosure Bulletin, Vol. 14, No. 10, 3/72, pp. 2983-2984.

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