Electrically addressable passive device, method for electrical a

Details Electrically addressable passive device, method for electrical a Electrically addressable passive device, method for electrical a

1999-02-12

2000-04-25

Nelms, David

Static information storage and retrieval

Systems using particular element

Semiconductive

243105, 243111, G11C 1136

Patent

active

060551801

DESCRIPTION:

BRIEF SUMMARY
FIELD OF THE INVENTION

The invention concerns an electrically addressable passive device for registration, storage and/or processing of data, wherein the device comprises a functional medium in the form of a substantially layer-like continuous or patterned structure, wherein the functional medium can undergo a physical or chemical change of state by a suitable energetic influence, wherein the functional medium comprises individually addressable passive cells provided in a two-dimensional pattern, and wherein a given physical or chemical state in a cell represent a registered or detected value or are assigned a predetermined logic value for the cell, and a method for electrical addressing of a passive device for registration, storing and/or processing of data, wherein the device comprises a functional medium in the form of a substantially layer-like continuous or patterned structure, wherein the functional medium can undergo a physical or chemical change of state by a suitable energetic influence, wherein the functional medium comprises individually addressable cells provided in a two-dimensional pattern, wherein a given physical or chemical state in a cell represent a registered or detected value or are assigned a predetermined logic value for the cell, wherein the addressing comprises operations for detection of a registered or detected value in the cell and additional operations for writing, reading, erasing and switching of a logical value assigned to the cell, and wherein the method comprises supplying electrical energy directly to the functional medium of the cell for detecting or changing the physical and/or chemical state of the cell and hence cause an addressing operation.
The invention also concerns uses of the electrically addressable passive device and the method for its electrical addressing.
Particularly the invention concerns a logic device which may be used for data memories of the ROM type, the WORM type or for realising a data memory which may be erased and written once more, and a method for addressing of such memories by purely electronic means.
Even more particularly the invention concerns addressing of data memories wherein the memory medium substantially consists of organic materials and the addressing takes place over a passive matrix of electrical conductors which contacts the memory medium directly or indirectly.


BACKGROUND OF THE INVENTION

Electronic addressing or logic devices, for instance for storage or processing of data are at present synonymous with inorganic solid state technology, and particularly crystalline silicon devices. Even if such devices have shown themselves technically and commercially very successful, they are encumbered with a number of disadvantages. Particularly they are encumbered with a complex architecture which leads to high cost and a loss of data storage density. Within the large subgroup of volatile semiconductor memories based on inorganic semiconductor material, the circuitry must constantly be supplied with electric current with a resulting heating and high electric power consumption in order to maintain the stored information. Non-volatile semiconductor devices on the other hand avoid this problem with a resulting reduction in the data rate accompanied by high power consumption and large degree of complexity. A number of different architectures has been implemented for memory chips based on semiconductor material and reflects a tendency to specialization with regard to different tasks. Matrix addressing of memory locations in a plane is a simple and effective way of achieving a great number of accessible memory locations with a reasonable number of lines for electrical addressing. In a square grid with n lines in each direction the number of memory locations hence scales as n.sup.2. In one form or another this is the basic principle which at present is implemented in a number of solid state semiconductor memories. In these cases however, each memory location must have a dedicated electronic circuit which communicates to the outside via the gri

REFERENCES:
patent: 3612758 (1971-10-01), Evans
patent: 3681754 (1972-08-01), Baasch
patent: 5592409 (1997-01-01), Nishimura et al.
patent: 5889694 (1999-03-01), Shepard
"Macromolecular Microstructures" Linkoping Studies in Science and Technology Dissertation No. 432, Linkoping 1996, pp. 49-51, 135-140 and 143-158.
"A new material for optical, electrical and electronic thin film memories" 1992 Pergamon Press Ltd., vol. 43, No. 11, pp. 1019-1023.

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