Active solid-state devices (e.g. – transistors – solid-state diode – Test or calibration structure
Reexamination Certificate
2000-02-15
2001-10-30
Bowers, Charles (Department: 2813)
Active solid-state devices (e.g., transistors, solid-state diode
Test or calibration structure
C438S018000
Reexamination Certificate
active
06310361
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of Invention
The invention relates to an electrical test structure in an integrated circuit, in particular in a DRAM circuit with trench capacitors. The invention further relates to a test method.
A multiplicity of process steps are necessary for fabricating an integrated circuit on a semiconductor substrate. A number of process steps during which a specific (partial) structure of the circuit is produced is referred to as a module; examples thereof are modules for forming isolation trenches in the substrate, for forming a transistor or for forming a capacitor. In order to identify defect sources, it is necessary to check individual process steps or complete modules in a suitable manner to ascertain whether prescribed specifications are being adhered to. It is thereby possible to use so-called “monitor wafers” (additional wafers on which the complete circuit is not fabricated) or the wafers with the partly completed circuits themselves. Optical or electrical test methods, inter alia, can be employed, the circuit itself or dedicated test structures being evaluated.
The present invention relates to a test method and a test structure which can be used, in particular, in the fabrication of DRAM memories with trench capacitors and a polysilicon strip (surface strap) as an electrical connection between the selection transistor and the capacitor, and will be explained in more detail using this example. The essential steps of the fabrication method or of the process module that is relevant in this case for the type of memory cells mentioned are illustrated in
FIGS. 5
to
8
. Provision is made (see
FIG. 5
) for forming, in a semiconductor substrate
1
, a trench
2
for a capacitor, whose wall is provided with a capacitor dielectric
3
in the lower section and with a thicker insulation collar
4
in the upper section. The trench is filled with doped polysilicon
5
a
,
5
b
as storage electrode. An isolation trench
6
is formed, which partly overlaps the trench and is filled with TEOS, for example. The isolation trench serves, in particular, to effect insulation from a neighboring cell which adjoins the memory cell illustrated in
FIG. 5
in a mirror-inverted manner on the right-hand side. The selection transistor is then formed adjacent to the capacitor trench
2
. A so-called gate stack comprising, in particular, n-doped polysilicon
8
, a further conductive layer
9
(for example WSi or another silicide) arranged thereon and a covering insulation layer
10
(for example made of silicon oxide or nitride) is formed on a gate oxide
7
. An insulating spacer
11
preferably made of the material of the covering insulation layer is produced on the sidewalls of the gate stack and the S/D regions
12
of the transistor are implanted. If appropriate, the spacer may be designed in two parts, LDD regions being implanted after the first spacer element in a known manner. The selection transistor of the memory cell is thus completed. A silicon nitride layer
13
is subsequently applied. The layer
13
has a preferred thickness in the range of from 20 to 30 nm.
The method further provides (see
FIG. 6
) for the nitride layer
13
to be removed, with the aid of a photomask, at the locations at which the surface straps for electrical connection between the selection transistor and the capacitor are intended to be formed. At the same time, the upper region of the trench capacitor is etched into and, in particular, the thick insulation collar is removed at that location down to a predetermined depth, thereby enabling contact with the capacitor here as well. The photomask thus has an opening above a region of the capacitor filling and the adjacent S/D region. The etching process employed (for example using CHF
3
/CF
4
and oxygen and argon) also attacks the covering insulating layer
10
and the side wall spacer
11
of the gate stack, so that there is a risk that the doped polysilicon
8
of the word line is uncovered. After the removal of the photomask, implantation using BF
2
ions, in particular, is performed; the remaining nitride
13
acts as a doping mask in this case. The opening in the nitride layer
13
corresponds to the opening in the photomask. It is essentially the case that uncovered silicon is p-doped—that is to say the region of the capacitor filing and the adjacent S/D region—while hardly any B
+
ions are deposited in uncovered silicon oxide. Afterwards, undoped polysilicon
14
is applied and p-doped section by section by means of outdiffusion from the underlying doped silicon and polysilicon. The polysilicon
14
thereby fills the hole produced in the trench. Its preferred thickness is from 50 to 100 nm.
The undoped polysilicon
14
is removed (see
FIG. 7
) by a KOH etching process or another suitable selective etching process which does not attack the p
+
-doped polysilicon sections
14
′ thus produced. The doped p
+
-type polysilicon sections
14
′ form the “surface straps”. There is a risk, however, of possibly uncovered n-doped polysilicon
8
of the gate likewise being attacked and removed. P
−
-doped silicon as a gate constituent would also be attacked by the etchant. This leads to the failure of the selection transistor (and hence of the memory cell) since a cavity is then produced above the gate oxide and the transistor cannot be driven, i.e., switched. It has been shown that the failing cells are usually distributed statistically and there exist correlations not just with one preceding process step, but with a number of preceding process steps.
The failure mechanism described leads to a dip in the yield. Electrical inline monitoring during the production process has not been possible heretofore, in particular as the problem generally occurs only in the cell array. There is an equally small possibility of unambiguously assigning the KOH attack to (subsequent) test data.
Further details of the method, only the essential points of which have been described here, are disclosed for example in U.S. Pat. No. 5,185,294 (European application EP 543 158 A2) and U.S. Pat. No. 5,731,218 (European application EP 651 433 A1—in particular columns 4 and 6 of the description).
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a test method and a test structure, which overcomes the above-mentioned disadvantages of the heretofore-known devices and methods of this general type and which enable real-time or inline monitoring, that is to say monitoring which accompanies the process.
With the foregoing and other objects in view there is provided, in accordance with the invention, a semiconductor structure, comprising:
a semiconductor substrate;
at least two MOS transistors formed in the semiconductor substrate;
each of the transistors having a gate with an n-doped or p
−
-doped polysilicon layer and a conductive layer disposed above the polysilicon layer, a first S/D region and a second S/D region, the gate having a covering insulation layer and insulating sidewall spacers;
the gates of the transistors being electrically connected to one another and having a terminal;
the second S/D region of a first one of the transistors being electrically connected to the first S/D region of a second one of the transistors; and
the first S/D region of the first transistor being connected to a first terminal and the second S/D region of the second transistor is connected to a second terminal.
In accordance with an added feature of the invention, the active regions of the transistors form a contiguous strip of monocrystalline silicon in the semiconductor substrate, and the first terminal and the second terminal are arranged near edges at opposite ends of the strip.
In accordance with an additional feature of the invention, a continuous, meandering word line runs over the strip, the word line containing the gates of the transistors.
In accordance with another feature of the invention, the conductive layer is composed of a silicide, preferably WSi.
With the above and other objects in view there is also pr
Bowers Charles
Greenberg Laurence A.
Infineon - Technologies AG
Lerner Herbert L.
Pert Evan
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