Electrical partitioning scheme for improving yields during the m

Static information storage and retrieval – Read/write circuit – Bad bit

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

G11C 1140

Patent

active

044894015

ABSTRACT:
Circuitry for isolating and rendering inoperative faulty storage devices in a semiconductor memory array is disclosed. A determination is made as to whether the x-addresses of the faulty storage devices contain an address bit having a common value for all of the faulty storage devices. If such an address bit exists, the address buffer associated with the common address bit is programmed to lock in a permanent set of address indicator outputs. All x-address locations accessed by address signals containing the common address bit are thereafter disabled. The memory array continues to function at half its former storage capacity, using the storage devices associated with the remaining address locations.

REFERENCES:
patent: 4250570 (1981-02-01), Tsang et al.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Electrical partitioning scheme for improving yields during the m does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Electrical partitioning scheme for improving yields during the m, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Electrical partitioning scheme for improving yields during the m will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-1991830

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.