Data processing: measuring – calibrating – or testing – Testing system – Signal generation or waveform shaping
Reexamination Certificate
2002-06-27
2004-10-19
Hoff, Marc S. (Department: 2857)
Data processing: measuring, calibrating, or testing
Testing system
Signal generation or waveform shaping
C702S058000, C324S500000, C324S522000
Reexamination Certificate
active
06807507
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to integrated circuit testers, and more particularly but not by limitation to integrated circuit testers for testing for electrical overstress.
BACKGROUND OF THE INVENTION
Semiconductor devices are typically designed to withstand a specified input voltage overstress, but due to fabrication process variations there is a potential that some devices within a large manufacturing lot will not meet the specification. Electrical overstress (EOS) is a leading cause of damage to integrated circuits. EOS of an integrated circuit generally results from an external source discharging large transient voltages, typically over a short period of time, over a terminal or pin of the integrated circuit. EOS events include very fast transients such as electrostatic discharge (ESD), and slower transients produced by power line glitches or dropouts.
Electrical spikes or transients are a key cause of electrical overstress in semiconductors, and in many cases these electrical spikes are unavoidable in electronic applications. There is a high probability that some of the semiconductor devices in a large sample will be weak and susceptible to partial damage during an electrical spike. This can be true even though the magnitude of the electrical pulse is within a specified range for the device. The amount of damage to the device caused by the electrical overstress is related to the electrical transient pulse width. Repetitive occurrences of these electrical transients will ultimately lead to permanent damage of the device.
There is a desire to find those devices that may fail early in the manufacturing process so that the overall product quality can be improved and the costs to reliably manufacture the product may be reduced. It is therefore desirable to identify, during the manufacturing process, those semiconductor devices that may fail at an abnormally high rate in normal operations. By removing those devices that may fail from reaching the end user, the manufacturer can reduce the number of customer returns due to failures, and therefore reduce their overall manufacturing costs. It is further desirable to identify those semiconductor devices that may fail as quickly and efficiently as possible to further reduce costs.
One prior art tester uses accelerated life testing, which electrically ages the semiconductor device in its final packaged form to identify defects that would result in premature failure of the device. Most processes used for testing semiconductor devices apply a temperature stress (heat) to bring a defective device to its failure point more quickly. These tests are often referred to as “burn-in” because of the use of heat. To generate this heat the device is either placed in an oven to provide an external heat source, or the heat source is placed in direct contact with the semiconductor device. The heat source may also be self-generated by electrically conditioning the device to an extreme electrical condition. Thus failures of defective devices can be occur in just a few hours of burn-in as opposed to months or years under normal conditions.
Burn-in testing of semiconductor devices still requires a few hours of testing to determine if a device is defective. Further, such tests do not necessarily detect a device that is susceptible to exposure due to electrical over stress.
Embodiments of the present invention provide solutions to these and other problems, and offer other advantages over the prior art.
SUMMARY OF THE INVENTION
The present invention is directed towards an apparatus for testing an integrated circuit for electrical over stress. The apparatus includes a spike source configured to couple to an input of the integrated circuit, and responsively provide a signal spike to the input, and a current sensor configured to couple to a power supply. The power supply is coupled to the integrated circuit to provide power to the integrated circuit, and the current sensor provides a sensor output related to the current supply to the integrated circuit from the power supply. The apparatus also includes test circuitry coupled to the sensor output configured to provide a failure output in response to an increase in the power supply current sensed by the current sensor in response to an applied signal spike.
Other features and benefits that characterize embodiments of the present invention will be apparent upon reading the following detailed description and review of the associated drawings.
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Kelly, M. et al. “Developing a Transient Induced Latch-up Standard for Testing Integrated Circcuits”, Sep. 1999, Electrical Overstress/Electrostatic Discharge Symposium Proceedings, 1999, Sep. 28-30, 1999. pp. 178-189.*
Kelly, M. et al. Developing a transient induced latch-up standard for testing integrated circuits, Sep. 1999, Electrical Overstress/Electrostatic Discharge Symposium Proceedings, 1999, Sep. 28-30, 1999. pp. 178-189.*
“Tester for Electrostatic-Discharge Faults in Integrated Circuits”, IBM Technical Disclosure Bulletin, Sep. 1985. vol. 28, Issue 4, pp. 1791-1792.
Dey Manoj Kumar
Kumar Vasudevan Seshadhri
Maung KyawSwa
Pooranakaran Pooranampillai Samuel
Barbee Manuel L
Hoff Marc S.
Westman Champlin & Kelly P.A.
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