Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates
Reexamination Certificate
2002-12-20
2004-11-09
Le, Don (Department: 2819)
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
C326S038000, C326S101000
Reexamination Certificate
active
06815982
ABSTRACT:
THE FIELD OF THE INVENTION
The present invention relates in general to the technical field of digital circuits and the design of their physical layout.
In particular, the present invention relates to an electrical or electronic circuit arrangement whose physical layout comprises
conductors and
cells associated with the conductors, such as flip-flop cells, buffer cells, inverter cells, logic gate cells and the like.
The present invention further relates to a method of producing at least one clock tree for the physical layout of an electrical or electronic circuit arrangement.
THE BACKGROUND ART
When electrical or electronic systems, and particularly electrical or electronic circuit arrangements, are being designed, there are certain steps in the procedure that are gone through repeatedly in a preset sequence; this is true both of microelectronic systems and also, in principle, of printed-circuit boards. Once the circuit or parts thereof have been designed with the help of a description in H[ardware] D[escription] L[anguage] or a graphic editor, this is normally followed by a first simulation to allow the functional behavior and, in the case of a bottom-up procedure, the behavior with time as well even at this early stage, to be verified.
If faults are found, the design is revised and tested again. Because the first simulation generally takes place before the physical layout is produced, it is also referred to as the pre-layout simulation. The parasitic capacitances and parasitic resistances on the connecting conductors that are to be laid down later are estimated in advance and the first simulation is carried out with these estimated values. In the present connection, the term “parasitics” will be borrowed from the specialist vocabulary accepted in the field of C[omputer] A[ided] E[engineering] and will be used to refer generally to such parasitic capacitances and resistances.
In the pre-layout simulation, many programs allow only for the already known number of inputs to other gates that are connected to a gate output or always cater for the maximum permitted capacitive load at a gate output, e.g. a capacitive load of 2 pF for a standard cell. In the first case the results tend to be optimistic and in the second pessimistic.
Once the physical layout of the microelectronic circuit or printed-circuit board has been prepared and has successfully passed the D[esign] R[ule] C[hecks] (DRC) or E[lectronic] R[ules] C[hecks] (ERC), the parasitics that will actually occur on the connecting conductors can be determined from it. So-called extraction programs for the netlists calculate the data that is wanted from the conductor geometries.
For chip design these programs are particularly complicated because the parasitic effects in the semiconductor structures themselves, such as source-drain capacitances and resistances, gate capacitances, contact resistances and the like, are extracted as well. Because the contours of the connection layers or implant regions in microelectronic circuits are very small in relation to their thickness, the parasitics are calculated separately by area and by the size of the structures and the individual results are added together.
As well as the task of extracting the parasitics from the finished physical layout, there is also an important verification task that the extraction programs for the netlists are called upon to perform. When standard cells are being designed at the level of the physical layout, it is very easy for errors to creep in, and for this reason it is important for there to be a possible way of extracting the netlist from the physical design.
In the technical field referred to above, something else that is widely familiar (and necessary) for the design of standard cells at the level of the physical layout is for the so-called clock tree to be adjusted to meet topological requirements in the physical layout of the circuit arrangement.
An adjustment process of this kind conventionally involves the replacement or insertion, or the deletion, of buffer cells and inverter cells of different sizes within the clock tree. This adjustment process also changes the topology of other cells that do not form part of the clock tree proper, because the area occupied by the cells that do form part of the clock tree changes as a result of the replacement or insertion, or deletion, of the buffer cells or inverter cells.
The changes described above affect the overall layout of the circuit arrangement to such a degree that there may again be a significant change in the behavior of signals with time in the logic that was freely laid out, which means that fresh corrections are needed to the signal paths concerned. In other words, what this means is that the adjustment of the clock tree necessarily entails behavior with time being re-verified for the entire design of the circuit arrangement.
The standard size of clock buffer cells and clock inverter cells has necessarily to be oriented to the maximum cell size needed, to give the clock-tree adjusting tool the freedom of maneuver it needs for optimization purposes. This results in an overall increase in the area occupied by the cells that form part of the clock tree.
SUMMARY OF THE INVENTION
Taking the disadvantages and inadequacies described above as a point of departure and with due consideration of the prior art outlined above, it is an object of the present invention to refine an electrical or electronic circuit arrangement of the above kind, and a method of generating at least one clock tree for the physical layout of an electrical or electronic circuit arrangement, in such a way that there is no need for the topology of any of the other cells outside the clock tree to be changed when the clock tree is being adjusted.
This object is achieved by an electrical or electronic circuit arrangement having the features specified in claim
1
and by a method having the features specified in claim
6
. Advantageous embodiments and useful refinements of the invention are detailed in the respective sets of subclaims.
Hence the present invention is based on the fact that, when the so-called clock tree, i.e. the branching tree by which clock signals are distributed to cells such as flip-flop cells or logic gate cells, is being generated for digital circuit arrangements, automatic data-processing means, and particularly automatic software means, operate on the netlist for the circuit arrangement. To adjust the individual clock-signal delays and to safeguard the timing as a whole, these software means alter both the delay applied by individual buffer cells and inverter cells situated on the clock signal path and also the driver power.
This concept includes the preferably exclusive use of special trimmable clock buffer cells or special trimmable clock inverter cells within a clock tree. This being the case, these clock buffer cells or clock inverter cells, which are preferably arranged to form so-called library cells, differ from one another, in a particularly advantageous embodiment, in respect of the delay applied to the signal and in respect of the driver power, in order to make it possible for the clock tree to be adjusted.
However, in accordance with the teaching of the present invention, all these clock buffer cells and/or clock inverter cells are preferably of a uniform extent, i.e. of a fixed standard size, to prevent the adjustment of the clock tree, i.e. the branching tree for the distribution of a clock signal, from affecting the topological arrangement of other cells in the layout.
Consequently, the process of adjusting the clock tree is neutral with respect to placement, i.e. topologically neutral adjustment of the clock tree is possible in accordance with the invention by means of the trimmable buffer (library) cells of fixed standard size and by means of the trimmable inverter (library) cells of fixed standard size. The clock buffer cells and clock inverter cells used have to be made available in
Koninklijke Philips Electronics , N.V.
Le Don
Zawilski Peter
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