Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2005-01-18
2005-01-18
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06845493
ABSTRACT:
The present invention enables the quantification of line end shortening by utilizing a pattern of multiple conductive paths, each conductive path can include a conductor at each end, each conductor connected to a separate contact with the contacts connected by a polysilicon conductor. The conductors can vary in length by a constant increment from conductive path to conductive path, beginning with a length that results in a significant overlap at the contacts to a length that results in a significant underlap at the contacts. Resistance measurements of each conductive path can be made until a change either to or from an “open” occurs; this is the point from which, using the constant increment, the LES can be characterized.
REFERENCES:
patent: 5751015 (1998-05-01), Corbett et al.
patent: 6118137 (2000-09-01), Fulford et al.
patent: 6391669 (2002-05-01), Fasano et al.
patent: 20030104685 (2003-06-01), Reinberg
Brinks Hofer Gilson & Lione
Infineon - Technologies AG
Siek Vuthe
Tat Binh
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