Electrical isolation in integrated circuits

Details Electrical isolation in integrated circuits Electrical isolation in integrated circuits

1994-12-21

1995-06-06

Carroll, J.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257371, 257373, 257509, H01L 2702

Patent

active

054225078

ABSTRACT:
A back biasing technique is provided for increasing the field inversion voltage between adjacent MOS transistors and for reducing parasitic capacitances in an integrated circuit. The use of a charge pump is avoided by connecting the body portions of the MOS transistors to ground and the sources of the MOS transistors to the anode of a diode, the cathode of which are connected to a reference voltage such as to ground. In this manner, the sources are back biased relative to the material in which they are formed by a diode forward voltage drop. This technique is particularly applicable to CMOS circuits operating from a 3.3 volt supply, with p-well doping densities in excess of 1.times.10.sup.17 atoms/cm.sup.3.

REFERENCES:
patent: 3865654 (1975-02-01), Chang et al.
patent: 4336489 (1982-06-01), Frederiksen
patent: 4476476 (1984-10-01), Yu et al.
patent: 4647956 (1987-03-01), Shrivastava et al.

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