Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Flip chip
Reexamination Certificate
2000-06-06
2001-12-25
Flynn, Nathan (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Flip chip
C257S686000, C257S738000, C361S779000, C439S067000
Reexamination Certificate
active
06333563
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to an electrical interconnection package and a method thereof. More particularly, the invention encompasses an invention that increases the fatigue life of a Ball Grid Array (BGA) electrical interconnection. This invention structurally couples at least one module to an organic interposer using a high modulus underfill material. The organic interposer is then joined to a organic board using standard joining processes. The inventive module can then be removed from the organic board at any time by removing the organic interposer using standard rework techniques.
BACKGROUND OF THE INVENTION
Ball Grid Arrays (BGA) are widely used to electrically and mechanically connect substrates (typically ceramic) carrying semiconductor chips to a card. The BGA commonly consists of an array of metal balls which are soldered to connecting pads on both the card and the substrate.
Typically, the card (which usually consists of an FR4 body material with internal copper wiring) will have a much greater coefficient of thermal expansion than will the ceramic substrate that it is attached to. Consequently, during operation, as the entire assembly becomes heated, there is a strain imposed upon the BGA connections due to these differential expansions of the card and substrate. With repeated on-off operating cycles, the BGA connections eventually fatigue and fail by creating an open circuit or a circuit of high resistance.
U.S. Pat. No. 5,535,526 (White), assigned to International Business Machines Corporation, Armonk, New York, the disclosure of which is incorporated herein by reference, teaches a chip connected to an organic chip carrier substrate via solder, and wherein the organic chip carrier substrate is connected to a circuit board via connect balls.
U.S. Pat. No. 5,691,041 (Frankeny), assigned to International Business Machines Corporation, Armonk, N.Y., the disclosure of which is incorporated herein by reference, teaches a chip connected to a printed circuit board via an interposer.
Therefore, there is a need in the art to have an interconnect package where a substrate secured to at least one chip, has at least one organic interposer secured to the substrate with at least one first interconnect material or a set of first interconnect materials and at least one organic board secured to an organic interposer using at least one second interconnect material or a set of second interconnect materials, wherein the first interconnect material or the set of first interconnect materials has an onset of melting that is substantially above the onset of melting of the second interconnect material or second set of materials. This is of course neither taught nor disclosed by the prior art.
PURPOSES AND SUMMARY OF THE INVENTION
The invention is a novel electrical interconnection package and a method thereof.
Therefore, one purpose of this invention is to provide a structure and a method for an electrical interconnection package.
Another purpose of this invention is to increase the fatigue life of a Ball Grid Array (BGA) electrical interconnection.
Still another purpose of this invention is to structurally couple at least one module to an organic interposer using a high modulus underfill material.
Yet another purpose of this invention is to join an organic interposer to an organic board.
Still yet another purpose of the invention is to be able to rework the inventive module by removing the organic interposer from the organic board.
Therefore, in one aspect this invention comprises a method of forming an interconnect package comprising the steps of:
(a) securing at least one first interconnect material to a substrate having a chip secured thereto,
(b) securing an organic interposer to said substrate via said first interconnect material, and
(c) securing an organic board to said organic interposer via at least one second interconnect material, and thereby forming said interconnect package.
In another aspect this invention comprises an interconnect structure comprising, a substrate secured to at least one chip, at least one organic interposer secured to said substrate with at least one first interconnect, and at least one organic board secured to said at least one organic interposer using at least one second interconnect.
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patent: 5477082 (1995-12-01), Buckley, III et al.
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patent: 5535526 (1996-07-01), White
patent: 5598033 (1997-01-01), Behlen et al.
patent: 5598036 (1997-01-01), Ho
patent: 5636104 (1997-06-01), Oh
patent: 5691041 (1997-11-01), Frankeny et al.
patent: 5729440 (1998-03-01), Jimarez et al.
patent: 6102710 (2000-08-01), Beilin et al.
patent: 06350259-A (1994-12-01), None
Call Anson J.
Courtney Mark G.
DeLaurentis Stephen A.
Farooq Mukta S.
Farooq Shaji
Flynn Nathan
Forde Remmon R.
International Business Machines - Corporation
Pepper Margaret A.
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