Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Passive components in ics
Reexamination Certificate
2000-06-16
2001-11-27
Thomas, Tom (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Passive components in ics
C257S528000, C257S530000, C438S215000, C438S281000, C438S333000
Reexamination Certificate
active
06323535
ABSTRACT:
BACKGROUND
1. Technical Field
This disclosure relates to fuses for semiconductor devices and more particularly, to electrical fuses with characteristics to enhance the efficiency of fuse programming.
2. Description of the Related Art
In semiconductor devices, fuses are employed in a variety of applications. For example, fuses are employed to enable redundant elements to be employed in the case of failures encountered on the semiconductor device. Some of these fuses are electrically programmable, i.e.; they are programmed by applying electric voltage or current. These electrically programmable fuses may be fabricated to include poly-silicide. Poly-silicide includes polycrystalline silicon and an overlayer of silicide, such as a metal silicide. The electrically programmable fuses typically include an appropriately shaped polysilicon layer that is silicided to obtain a poly-silicon/metal silicide stack structure.
Referring to
FIG. 1
, a layout (shape) of a fuse
10
is shown. Fuse
10
includes a fuse link
12
, an anode
14
and a cathode
16
. Current crowding takes place around a location
18
where the fuse link
12
abuts the cathode
16
, when a bias is applied to set or program the fuse. When a poly-silicide fuse is programmed, the cathode is negatively biased and the anode is positively biased. The current crowding initiates electro-migration effects at the fuse link
12
resulting in further current crowding and finally for appropriate bias conditions, the poly-silicide line melts or the silicide agglomerates to result in an open circuit or a high resistance state (i.e., the fuse gets programmed) at the location
18
. The effect of material migration due to, for example, electro-migration can be increased at the cathode-fuse link junction by increasing the ratio of L
cathode
to L
fuse
, as this encourages current crowding. In typical layouts, the thickness of the fuse link
12
, the anode
14
and the cathode
16
are the same thickness because they are formed on the same level. Therefore, the lengths of L
cathode
and L
fuse
are determinative of the effective cross-sectional area of the fuse link/anode intersection. A polysilicon layer
20
and a silicide layer
22
as shown in
FIG. 2
are provided at a uniform thickness for the fuse link
12
, the anode
14
and the cathode
16
. A nitride capping layer
24
is also provided over layers
20
and
22
. Typical electrically programmable fuses require current flow and voltage levels at an appropriate level for a requisite amount of time to program the fuse.
Therefore, a need exists for an apparatus and method to initiate and aid mass transport processes near a fuse link/cathode intersection to reduce the programming current, voltage and time. These reductions are desirable for the electrical fuse technology to minimize energy consumption and the cost of programming fuses.
SUMMARY OF THE INVENTION
A fuse for semiconductor devices, in accordance with the present invention, includes a cathode including a first dopant type, and an anode including a second dopant type where the second dopant type is opposite the first dopant type. A fuse link connects the cathode and the anode and includes the second dopant type. The fuse link and the cathode form a junction therebetween, and the junction is configured to be reverse biased relative to a cathode potential and an anode potential. A conductive layer is formed across the junction such that current flowing at the junction is diverted into the conductive layer to enhance material migration to program the fuse.
Another fuse for semiconductor devices includes a conductive pattern formed on a substrate. The conductive pattern forms a cathode on a first end portion. A fuse link connects the cathode and an anode, and the anode is formed on a second end portion of the conductive pattern. The fuse link and the cathode form a junction therebetween. A conductive layer is formed across the junction such that when the fuse is electrically active the junction is reverse biased and material migration is enhanced to program the fuse.
Yet, another fuse for semiconductor devices includes a polysilicon pattern formed on a substrate. The polysilicon pattern forms a p-doped cathode on a first end portion. An n-doped fuse link connects the cathode and an anode. The anode is formed on a second end portion of the polysilicon pattern. A reverse biased junction is formed at the interface between the cathode and the fuse link. A silicide material is formed across the junction, such that, when the fuse is electrically active, current is diverted from the reverse biased junction into the silicide material to enhance electromigration and program the fuse.
In alternate embodiments, the cathode, anode and fuse link preferably include polysilicon. The conductive layer preferably includes a silicide. The first dopant type may include a p type dopant and the second dopant type includes an n type dopant. The cathode preferably has a larger cross-sectional area than the fuse link. The cathode and the fuse link may provide an interface of the junction, which is substantially perpendicular to a current flow direction through the fuse link. The polysilicon of the cathode is preferably p-doped, and the polysilicon of the fuse link is preferably n-doped.
These and other objects, features and advantages of the present invention will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings.
REFERENCES:
patent: 3975683 (1976-08-01), Behrens et al.
patent: 4517583 (1985-05-01), Uchida
patent: 5661331 (1997-08-01), Hebbeker et al.
patent: 1-169942-A (1989-07-01), None
Brintzinger Axel
Iyer Subramanian
Iyer Sundar K.
Narayan Chandrasekhar
Smeys Peter
Braden Stanton C.
Infineon Technologies North America Corp.
Kang Donghee
Thomas Tom
LandOfFree
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